fix(security): add CVE-2025-0647 for Cortex-X2

This patch mitigates CVE-2025-0647 for Cortex-X2 CPU.

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: Idba6

fix(security): add CVE-2025-0647 for Cortex-X2

This patch mitigates CVE-2025-0647 for Cortex-X2 CPU.

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: Idba607340d944a6387759c856e8eacc967e0ec06
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): add CVE-2025-0647 for Cortex-A710

This patch mitigates CVE-2025-0647 for Cortex-A710 CPU.

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: I

fix(security): add CVE-2025-0647 for Cortex-A710

This patch mitigates CVE-2025-0647 for Cortex-A710 CPU.

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: I522dedfffd3108f7a94df1ce2cabd742ce682334
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>

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feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will

feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will ask to have Core 1 available. The PSCI platform
code is done in stm32_pwr_domain_on(). Core0 will change Core1 reset
address thanks to CA35SS_SYSCFG_VBAR_CR register to BL31 entry point.
And will reset Core1 by setting RCC_C1P1RSTCSETR_C1P1PORRST bit.
It is possible to turn core 1 on and off. But it is not possible to do
so on core 0.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I01e59e3a2398c48cc050ec4703d6610da9e9c4bd

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Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add

Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add DDR training stubs

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feat(build): add HOSTLDFLAGS to pass flags to host links

There is a HOSTCCFLAGS variable to pass flags to all host compilations,
but no corresponding HOSTLDFLAGS to pass flags to host links.

Change

feat(build): add HOSTLDFLAGS to pass flags to host links

There is a HOSTCCFLAGS variable to pass flags to all host compilations,
but no corresponding HOSTLDFLAGS to pass flags to host links.

Change-Id: I17441fc61e45d2ee41f9ab55a5d745bd0d2156d7
Signed-off-by: Ross Burton <ross.burton@arm.com>

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feat(st): add stm32mp_gic_cpuif_enable/disable

Add function to enable and disable GIC dispatcher when it is necessary
in pm functions.

Change-Id: I2fe22b3728577d3fc1292e7db7afe7183aa3fc9a
Signed-of

feat(st): add stm32mp_gic_cpuif_enable/disable

Add function to enable and disable GIC dispatcher when it is necessary
in pm functions.

Change-Id: I2fe22b3728577d3fc1292e7db7afe7183aa3fc9a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc85

feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc8579b0728db3feb5

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feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id:

feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id: I10bda7930bd809640f2b40fe46a6fa568946c09d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(st): add STM32MP_SUPPORT_PM flag

This flag will be used to enable low power features.

Change-Id: I45d2b6b2ed1da9259a654359f6e611813f92a9c9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

feat(st): disable FWU on serial boot devices

When compiling for USB or UART boot devices, it makes no sense to
enable Firmware update through PSA_FWU_SUPPORT=1.
In this case force the flag to 0, to

feat(st): disable FWU on serial boot devices

When compiling for USB or UART boot devices, it makes no sense to
enable Firmware update through PSA_FWU_SUPPORT=1.
In this case force the flag to 0, to avoid compilation issues.

Change-Id: Id7e35754fd9cf3fb3c26b8ccb947bd39c981231e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(drtm): map DLME and DRTM parameter region as execute-never

Replace MT_MEMORY | MT_NS | MT_RO with MT_NS | MT_RO_DATA for the DRTM
parameter and DLME dynamic mappings. This maps the regions as re

fix(drtm): map DLME and DRTM parameter region as execute-never

Replace MT_MEMORY | MT_NS | MT_RO with MT_NS | MT_RO_DATA for the DRTM
parameter and DLME dynamic mappings. This maps the regions as read-only
data and execute-never. This is as per DRTM specification.

Change-Id: I3e0f555e9a26726389a7c5f6b4fef65cb4078ee2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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chore: bump event log library

Refactor and addition of new event type: EV_SECURITY_CONFIG

Change-Id: Id75c98334a110417845798a1f01305fa8ea2f05c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.

chore: bump event log library

Refactor and addition of new event type: EV_SECURITY_CONFIG

Change-Id: Id75c98334a110417845798a1f01305fa8ea2f05c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status
feat(cpufeat): advertise support for FEAT_RASv2
feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

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Merge changes from topic "xl/c1-workaround-fix" into integration

* changes:
fix(cpus): fix the ordering of errata for C1 Premium
fix(cpus): fix the ordering of errata for C1 Ultra

Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpu

Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

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Merge "fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1" into integration

fix(cpus): fix the ordering of errata for C1 Premium

Reorder the errata to comply with the convention.

Change-Id: Ifd1c73224060c1c2e94c5f7978e9dc79e0229bd4
Signed-off-by: Xialin Liu <xialin.liu@arm

fix(cpus): fix the ordering of errata for C1 Premium

Reorder the errata to comply with the convention.

Change-Id: Ifd1c73224060c1c2e94c5f7978e9dc79e0229bd4
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): fix the ordering of errata for C1 Ultra

The CVE workaround is placed before errata workaround,
fix it to comply with the convention.

Change-Id: I6482ce4015541c64d9ac0d9c9df2e84d0c9eaae0

fix(cpus): fix the ordering of errata for C1 Ultra

The CVE workaround is placed before errata workaround,
fix it to comply with the convention.

Change-Id: I6482ce4015541c64d9ac0d9c9df2e84d0c9eaae0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(build): assign the ldflags-common variable before appending to it" into integration

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now integrated into
the DDR initialization flow.

Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge "refactor(psci): make CMOs target the whole psci_cpu_data_t" into integration

feat(rdv3): use SFCP PSA call instead of RSE comms

In a similar manner to the TC platform, add the SFCP platform
definitions for RDV3. SFCP is then used instead of RSE comms for making
PSA calls int

feat(rdv3): use SFCP PSA call instead of RSE comms

In a similar manner to the TC platform, add the SFCP platform
definitions for RDV3. SFCP is then used instead of RSE comms for making
PSA calls into the RSE.

Change-Id: I6deddab452026ba24bd2462bcf2f11846af6f80b
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the

feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the device structures and also the routing tables.

Note that, because initially the SFCP stack is only used to make PSA
calls to the RSE, routing is only implemented for the TF-A <-> RSE
nodes. The only MHU devices defined in the SFCP platform implementation
are for this link and all other routes, as defined in the routing table,
as invalid.

This patch also removes compilation of RSE comms in favour of SFCP for
TC.

Change-Id: I432b05b2955c790c4a5ecff04764605c6ff0ceea
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions

feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions are expected to be implemented by any TF-A
platform which makes use of the SFCP library, they define the underlying
device driver structures and the routing layout of the platform.

Change-Id: I4af7371decd1faabbd0ed7bc186339668a0c6b1a
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(sfcp): add SFCP stack and PSA call

Add SFCP stack from trusted-firmware-m commit 8eb72a3bc5cc. SFCP is the
Simple Firmware Communication Protocol, which is a more substantial
software stack des

feat(sfcp): add SFCP stack and PSA call

Add SFCP stack from trusted-firmware-m commit 8eb72a3bc5cc. SFCP is the
Simple Firmware Communication Protocol, which is a more substantial
software stack designed to replace the existing RSE comms (and indeed
wider communication between firmware components in the system). It has
support for both polling mode and interrupt driver communication
handling, and is able to support any underlying transport (this patch
adds MHU only). It requires a static routing layout between system
components.

This patch adds the link layer (with support for the MHU transport),
top-level SFCP API implementation and the implementation of PSA
call making use of the SFCP API.

Note that encryption support is not implemented and only the stub
encryption implementation is added in this patch. This can be
implemented when TF-A needs it.

The sfcp_link_hal.c implementation is the same as that in
trusted-firmware-m, and it makes use of the MHU V2 and V3 drivers
directly. This is possible as the underlying MHU driver APIs is the same
in trusted-firmware-m and trusted-firmware-a.

Change-Id: I2318ea4bdb4e533b8a4a5000040aec0635a83857
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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