1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#include <dsu_macros.S> 15#include <wa_cve_2025_0647_cpprctx.h> 16 17#include <plat_macros.S> 18 19/* Hardware handled coherency */ 20#if HW_ASSISTED_COHERENCY == 0 21#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 22#endif 23 24/* 64-bit only core */ 25#if CTX_INCLUDE_AARCH32_REGS == 1 26#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 27#endif 28 29.global check_erratum_cortex_a710_3701772 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35cpu_reset_prologue cortex_a710 36 37workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 38 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 39workaround_reset_end cortex_a710, ERRATUM(1901946) 40 41check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 42 43workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945 44 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 45workaround_reset_end cortex_a710, ERRATUM(1916945) 46 47check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0) 48 49workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258 50 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43) 51workaround_reset_end cortex_a710, ERRATUM(1917258) 52 53check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0) 54 55workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200 56 mov x0, #0 57 msr S3_6_C15_C8_0, x0 58 ldr x0, =0x10E3900002 59 msr S3_6_C15_C8_2, x0 60 ldr x0, =0x10FFF00083 61 msr S3_6_C15_C8_3, x0 62 ldr x0, =0x2001003FF 63 msr S3_6_C15_C8_1, x0 64 65 mov x0, #1 66 msr S3_6_C15_C8_0, x0 67 ldr x0, =0x10E3800082 68 msr S3_6_C15_C8_2, x0 69 ldr x0, =0x10FFF00083 70 msr S3_6_C15_C8_3, x0 71 ldr x0, =0x2001003FF 72 msr S3_6_C15_C8_1, x0 73 74 mov x0, #2 75 msr S3_6_C15_C8_0, x0 76 ldr x0, =0x10E3800200 77 msr S3_6_C15_C8_2, x0 78 ldr x0, =0x10FFF003E0 79 msr S3_6_C15_C8_3, x0 80 ldr x0, =0x2001003FF 81 msr S3_6_C15_C8_1, x0 82workaround_reset_end cortex_a710, ERRATUM(1927200) 83 84check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0) 85 86workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 87 ldr x0,=0x6 88 msr S3_6_c15_c8_0,x0 89 ldr x0,=0xF3A08002 90 msr S3_6_c15_c8_2,x0 91 ldr x0,=0xFFF0F7FE 92 msr S3_6_c15_c8_3,x0 93 ldr x0,=0x40000001003ff 94 msr S3_6_c15_c8_1,x0 95 ldr x0,=0x7 96 msr S3_6_c15_c8_0,x0 97 ldr x0,=0xBF200000 98 msr S3_6_c15_c8_2,x0 99 ldr x0,=0xFFEF0000 100 msr S3_6_c15_c8_3,x0 101 ldr x0,=0x40000001003f3 102 msr S3_6_c15_c8_1,x0 103workaround_reset_end cortex_a710, ERRATUM(1987031) 104 105check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 106 107workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 108 /* Stash ERRSELR_EL1 in x2 */ 109 mrs x2, ERRSELR_EL1 110 111 /* Select error record 0 and clear ED bit */ 112 msr ERRSELR_EL1, xzr 113 mrs x1, ERXCTLR_EL1 114 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 115 msr ERXCTLR_EL1, x1 116 117 /* Select error record 1 and clear ED bit */ 118 mov x0, #1 119 msr ERRSELR_EL1, x0 120 mrs x1, ERXCTLR_EL1 121 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 122 msr ERXCTLR_EL1, x1 123 124 /* Restore ERRSELR_EL1 from x2 */ 125 msr ERRSELR_EL1, x2 126workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 127 128check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 129 130workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 131 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 132workaround_reset_end cortex_a710, ERRATUM(2017096) 133 134check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 135 136workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 137 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 138workaround_reset_end cortex_a710, ERRATUM(2055002) 139 140check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 141 142workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 143 ldr x0,=0x3 144 msr S3_6_c15_c8_0,x0 145 ldr x0,=0xF3A08002 146 msr S3_6_c15_c8_2,x0 147 ldr x0,=0xFFF0F7FE 148 msr S3_6_c15_c8_3,x0 149 ldr x0,=0x10002001003FF 150 msr S3_6_c15_c8_1,x0 151 ldr x0,=0x4 152 msr S3_6_c15_c8_0,x0 153 ldr x0,=0xBF200000 154 msr S3_6_c15_c8_2,x0 155 ldr x0,=0xFFEF0000 156 msr S3_6_c15_c8_3,x0 157 ldr x0,=0x10002001003F3 158 msr S3_6_c15_c8_1,x0 159workaround_reset_end cortex_a710, ERRATUM(2081180) 160 161check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 162 163workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 164 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 165workaround_reset_end cortex_a710, ERRATUM(2083908) 166 167check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 168 169workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 170 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 171workaround_reset_end cortex_a710, ERRATUM(2136059) 172 173check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 174 175workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 176 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 177workaround_reset_end cortex_a710, ERRATUM(2147715) 178 179check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 180 181workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 182 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 183 184 ldr x0,=0x5 185 msr CORTEX_A710_CPUPSELR_EL3, x0 186 ldr x0,=0x10F600E000 187 msr CORTEX_A710_CPUPOR_EL3, x0 188 ldr x0,=0x10FF80E000 189 msr CORTEX_A710_CPUPMR_EL3, x0 190 ldr x0,=0x80000000003FF 191 msr CORTEX_A710_CPUPCR_EL3, x0 192workaround_reset_end cortex_a710, ERRATUM(2216384) 193 194check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 195 196workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 197 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 198workaround_reset_end cortex_a710, ERRATUM(2267065) 199 200check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 201 202workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 203 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 204workaround_reset_end cortex_a710, ERRATUM(2282622) 205 206check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 207 208.global erratum_cortex_a710_2291219_wa 209workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 210 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 211 * the workaround. Second call clears it to undo it. */ 212 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 213workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 214 215check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 216 217workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 218 errata_dsu_2313941_wa_impl 219workaround_reset_end cortex_a710, ERRATUM(2313941) 220 221check_erratum_custom_start cortex_a710, ERRATUM(2313941) 222 check_errata_dsu_2313941_impl 223 ret 224check_erratum_custom_end cortex_a710, ERRATUM(2313941) 225 226workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 227 /* Set bit 40 in CPUACTLR2_EL1 */ 228 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 229workaround_reset_end cortex_a710, ERRATUM(2371105) 230 231check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 232 233workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 234 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 235 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 236 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 237workaround_reset_end cortex_a710, ERRATUM(2742423) 238 239check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 240 241workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 242 /* dsb before isb of power down sequence */ 243 dsb sy 244workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 245 246check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 247 248workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 249 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 250workaround_reset_end cortex_a710, ERRATUM(2778471) 251 252check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 253 254workaround_runtime_start cortex_a710, ERRATUM(3324338), ERRATA_A710_3324338 255 speculation_barrier 256workaround_runtime_end cortex_a710, ERRATUM(3324338) 257 258check_erratum_ls cortex_a710, ERRATUM(3324338), CPU_REV(2, 1) 259 260add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 261 262check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 263 264workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 265#if IMAGE_BL31 266 /* 267 * The Cortex-A710 generic vectors are overridden to apply errata 268 * mitigation on exception entry from lower ELs. 269 */ 270 override_vector_table wa_cve_vbar_cortex_a710 271#endif /* IMAGE_BL31 */ 272workaround_reset_end cortex_a710, CVE(2022, 23960) 273 274check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 275 276/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 277workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 278 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 279workaround_reset_end cortex_a710, CVE(2024, 5660) 280 281check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 282 283 /* 284 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 285 * Enables mitigation for CVE-2025-0647. 286 */ 287workaround_reset_start cortex_a710, CVE(2025, 647), WORKAROUND_CVE_2025_0647 288 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) 289 bl wa_cve_2025_0647_instruction_patch 290workaround_reset_end cortex_a710, CVE(2025, 647) 291 292check_erratum_chosen cortex_a710, CVE(2025, 647), WORKAROUND_CVE_2025_0647 293 294#if WORKAROUND_CVE_2025_0647 295func cortex_a710_impl_defined_el3_handler 296 mov x0, #WA_LS_RCG_EN 297 298 /* See if this call came from trap handler. */ 299 cmp x1, #EC_IMP_DEF_EL3 300 bne wa_cve_2025_0647_do_cpp_wa 301 orr x0, x0, #WA_IS_TRAP_HANDLER 302 b wa_cve_2025_0647_do_cpp_wa 303endfunc cortex_a710_impl_defined_el3_handler 304#endif 305 306 /* ---------------------------------------------------- 307 * HW will do the cache maintenance while powering down 308 * ---------------------------------------------------- 309 */ 310func cortex_a710_core_pwr_dwn 311 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 312 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 313 314 /* --------------------------------------------------- 315 * Enable CPU power down bit in power control register 316 * --------------------------------------------------- 317 */ 318 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 319 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 320 isb 321 ret 322endfunc cortex_a710_core_pwr_dwn 323 324cpu_reset_func_start cortex_a710 325 /* Disable speculative loads */ 326 msr SSBS, xzr 327 apply_erratum cortex_a710, ERRATUM(3324338), ERRATA_A710_3324338 328 329 enable_mpmm 330cpu_reset_func_end cortex_a710 331 332 /* --------------------------------------------- 333 * This function provides Cortex-A710 specific 334 * register information for crash reporting. 335 * It needs to return with x6 pointing to 336 * a list of register names in ascii and 337 * x8 - x15 having values of registers to be 338 * reported. 339 * --------------------------------------------- 340 */ 341.section .rodata.cortex_a710_regs, "aS" 342cortex_a710_regs: /* The ascii list of register names to be reported */ 343 .asciz "cpuectlr_el1", "" 344 345func cortex_a710_cpu_reg_dump 346 adr x6, cortex_a710_regs 347 mrs x8, CORTEX_A710_CPUECTLR_EL1 348 ret 349endfunc cortex_a710_cpu_reg_dump 350 351#if WORKAROUND_CVE_2025_0647 352declare_cpu_ops_eh cortex_a710, CORTEX_A710_MIDR, \ 353 cortex_a710_reset_func, \ 354 cortex_a710_impl_defined_el3_handler, \ 355 cortex_a710_core_pwr_dwn 356#else 357declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 358 cortex_a710_reset_func, \ 359 cortex_a710_core_pwr_dwn 360#endif 361