fix(spe): invoke spe_disable during power domain off/suspend

spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to

fix(spe): invoke spe_disable during power domain off/suspend

spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to be invoked as SPE feature writes to memory as part of
regular operation and not disabling before exiting coherency
could potentially cause issues.

Currently, this is handled only for the FVP. Other platforms need
to replicate this behaviour and is covered as part of this patch.

Calling it from generic psci library code, before the platform specific
actions to turn off the CPUs, will make it applicable for all the
platforms which have ported the PSCI library.

Change-Id: I90b24c59480357e2ebfa3dfc356c719ca935c13d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(psci): add psci_do_manage_extensions API

Adding a new API under PSCI library,for managing all the architectural
features, required during power off or suspend cases.

Change-Id: I1659560daa43b9

feat(psci): add psci_do_manage_extensions API

Adding a new API under PSCI library,for managing all the architectural
features, required during power off or suspend cases.

Change-Id: I1659560daa43b9344dd0cc0d9b311129b4e9a9c7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In realit

fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In reality we barely see implementations with two PEs per core, and
didn't have four at all so far.

With some design changes we now include more data per CPU type, and
since the Arm FPGA build supports many cores (and determines the correct
one at runtime), we run out of memory with certain build options.

Since we don't really need four PEs per core, just halve that number, to
reduce our memory footprint without sacrificing functionality.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieb37ccc9f362b10ff0ce038f72efca21512a71cb

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feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detaile

feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detailed steps are documented as comments in the relevant source
files introduced in this patch.

Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): initialize SCR_EL3.EEL2 bit at RESET

SCR_EL3.EEL2 bit enabled denotes that the system has S-EL2 present and
enabled, Ideally this bit is constant throughout the lifetime and
should not b

feat(spmd): initialize SCR_EL3.EEL2 bit at RESET

SCR_EL3.EEL2 bit enabled denotes that the system has S-EL2 present and
enabled, Ideally this bit is constant throughout the lifetime and
should not be modified. Currently this bit is initialized in the context
mgmt code where each world copy of the SCR_EL3 register has this bit set
to 1, but for the time duration between the RESET and the first exit to
a lower EL this bit is zero.

Modifying SCR_EL3.EEL2 along with EA bit at RESET does also helps in
mitigating against ERRATA_V2_3099206.

For details on Neoverse V2 errata 3099206, refer the SDEN document
given below.
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If8b2bdbb19bc65391a33dd34cc9824a0203ae4b1

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docs(auth): add missing AUTH_PARAM_NV_CTR value

Section "Describing the authentication method(s)" of the Authentication
Framework documentation shows the authentication parameters types
(auth_param_

docs(auth): add missing AUTH_PARAM_NV_CTR value

Section "Describing the authentication method(s)" of the Authentication
Framework documentation shows the authentication parameters types
(auth_param_type_t enum type) but is missing the AUTH_PARAM_NV_CTR
value. Add it.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I7c9022badfb039bfa9f999ecee40f18b49e6764c

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docs: fix link to TBBR specification

The former link pointed to a page which displayed the following warning
message:

We could not find that page in the latest version, so we have taken
you to

docs: fix link to TBBR specification

The former link pointed to a page which displayed the following warning
message:

We could not find that page in the latest version, so we have taken
you to the first page instead

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Icf9277770e38bc5e602b75052c2386301984238d

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refactor(build): minor updates

Move RME to 9.2 optional features and add minor updates to comments.

Change-Id: I12a4940e82ca5df72af5421ddab43bc6a1628e95
Signed-off-by: Govindraj Raja <govindraj.raj

refactor(build): minor updates

Move RME to 9.2 optional features and add minor updates to comments.

Change-Id: I12a4940e82ca5df72af5421ddab43bc6a1628e95
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(build): remove enabling feat

All mandatory FEAT_* enabling is done from arch_features.mk.
Remove some old code which would enable some mandatory options based
on arch-features option passed

refactor(build): remove enabling feat

All mandatory FEAT_* enabling is done from arch_features.mk.
Remove some old code which would enable some mandatory options based
on arch-features option passed to march appending.

This is now not needed anymore since if we are using correct
ARCH_MAJOR/MINOR the mandatory options will taken care from
arch_features.mk

Change-Id: I8565ac4ebb3ced29835be65ea5b043a08810872f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(build): march handling with arch-features

Currently all march compiler option handling is moved to build
utility in march.mk.

We pass arch-features to build which appends to march options,
so t

fix(build): march handling with arch-features

Currently all march compiler option handling is moved to build
utility in march.mk.

We pass arch-features to build which appends to march options,
so this should be done once we decide march options and moving
it to march.mk file.

Change-Id: Ifaf99af5f371fd28db376a12657ccf4f363295c2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(build): refactor mandatory options

Currently we enable all mandatory options for a current MAJOR.MINOR
number without considering architecturally to what version the current
arch should be

refactor(build): refactor mandatory options

Currently we enable all mandatory options for a current MAJOR.MINOR
number without considering architecturally to what version the current
arch should be compliant with.

For example Arch v9 should be compliant with 8.5 and shouldn't
consider being compliant with 8.9, so refactor FEAT_* handling to
ensure we capture and handle compliance correctly.

So refactor to use a list and add FEAT_* which are only compliant
with a given arch rather than relying on all the FEAT_* from previous
should be enabled for given arch version.

Change-Id: I8b0dd076c168a647de43b8618fbbe607412f7cab
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "refactor(build): allow mandatory feats disabling" into integration

Merge "feat(cros_widevine): add ChromeOS widevine SMC handler" into integration

Merge "docs(contributing): various improvements" into integration

Merge "fix(libc): memset inclusion to libc makefiles" into integration

fix(scmi): induce a delay in monitoring SCMI channel status

Reading the SCMI mailbox status in polling mode causes a burst of bus
accesses. On certain platforms, this would not be ideal as the share

fix(scmi): induce a delay in monitoring SCMI channel status

Reading the SCMI mailbox status in polling mode causes a burst of bus
accesses. On certain platforms, this would not be ideal as the shared
bus on the CPU subsystem might cause contentions across all the CPUs.
So allow platforms to specify a delay to be introduced while polling.

Change-Id: Ib90ad7b5954854071cfd543f4a27a178dde3d5c6
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a5

feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a54b489c6
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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fix(libc): memset inclusion to libc makefiles

Fix [1] is introducing another problem in that memset is added twice to
the libc makefile when OVERRIDE_LIBC=1 (the C and asm implementations).

Correct

fix(libc): memset inclusion to libc makefiles

Fix [1] is introducing another problem in that memset is added twice to
the libc makefile when OVERRIDE_LIBC=1 (the C and asm implementations).

Correct by adding memset.c when OVERRIDE_LIBC=0 and memset.S when
OVERRIDE_LIBC=1.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26091

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie4b7e04880d4cd871e7b51cd8ff5bddcf8d0308c

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feat(cros_widevine): add ChromeOS widevine SMC handler

The ChromeOS will use the SMC to pass some secrets from firmware to
optee.

Change-Id: Iaf3357d40a7ed22415926acd9d7979df24dd81f1
Signed-off-by:

feat(cros_widevine): add ChromeOS widevine SMC handler

The ChromeOS will use the SMC to pass some secrets from firmware to
optee.

Change-Id: Iaf3357d40a7ed22415926acd9d7979df24dd81f1
Signed-off-by: Yi Chou <yich@google.com>

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fix(k3): increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data and not
get the end

fix(k3): increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data and not
get the end data corrupted from secure proxy.

Fixes: d76fdd33e011 ("ti: k3: drivers: Add Secure Proxy driver")

Change-Id: I8e23f8b6959da886d6ab43049746f78765ae1766
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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Merge "fix(ehf): restrict secure world FIQ routing model to SPM_MM" into integration

fix(ehf): restrict secure world FIQ routing model to SPM_MM

Exception handling framework (EHF) changes the semantics of interrupts,
sync and async external aborts. As far as interrupts are concerned

fix(ehf): restrict secure world FIQ routing model to SPM_MM

Exception handling framework (EHF) changes the semantics of interrupts,
sync and async external aborts. As far as interrupts are concerned it
changes the routing model of foreign interrupts (FIQs) by changing
SCR_EL3.FIQ to 1 for both non-secure and secure except when SPMD is
used along with Hafnium/SPM at S-EL2 [1].
For NS world it means : G1S and G0 interrupts are routed to EL3
For Secure world it means : G1NS and G0 are routed to EL3

There is no upstream use case utilizing EHF and re-routing EL3
interrupts to the Secure world except when SPM_MM is present.

Modify the FIQ routing model during EHF init just for known use cases,
Always for NS world and for secure world only if SPM_MM is present.

[1]:https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic292bbe8dd02d560aece5802d79569d868d8500f

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Merge "fix(build): mute sp_mk_generator from build log" into integration

fix(build): mute sp_mk_generator from build log

Add a silent token to sp_mk_generator python script invocation.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51d9bd6965504d8869

fix(build): mute sp_mk_generator from build log

Add a silent token to sp_mk_generator python script invocation.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51d9bd6965504d8869e946db0a74691bbaa1dcd2

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Merge "fix(cpus): workaround for Cortex X3 erratum 2641945" into integration