Merge "feat(stm32mp15): remove OP-TEE shared mem" into integration

Merge "feat(tc): add default SLC policy for the gpu" into integration

Merge "feat(tc): support full-HD resolution for the FVP model" into integration

feat(fvp): fdts: add stdout-path to the Foundation FVPs

Add an `stdout-path' property into the `chosen' node of the Foundation
FVPs Devicetrees.

This gives a default console to the Linux kernel whe

feat(fvp): fdts: add stdout-path to the Foundation FVPs

Add an `stdout-path' property into the `chosen' node of the Foundation
FVPs Devicetrees.

This gives a default console to the Linux kernel when "console=" is not
specified on the kernel command line, which is useful when booting with
U-Boot in UEFI for example.

Change-Id: I27d5f7f9416bd42b7401b1a57ae64bfee2524204
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>

show more ...

Merge "chore(errata-abi): minor variable rename" into integration

chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr v

chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.

So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.

Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3 for TC3
feat(tc): add MHUv3 DT binding for TC3
feat(tc): add MHUv3 doorbell support on TC3
refactor(tc): change tc_scmi_plat_info to single structure

show more ...

feat(tc): add default SLC policy for the gpu

As per the GPU integration guide, adding the PBHA INT overrides to
influence the GPU allocation policy for the System Level Cache (SLC).

This commit use

feat(tc): add default SLC policy for the gpu

As per the GPU integration guide, adding the PBHA INT overrides to
influence the GPU allocation policy for the System Level Cache (SLC).

This commit uses SLC policy #23, which is the Arm SLC cache policy
number for GPUs. The cache policy #23 may not be optimal for all
workloads, although it outperforms other policies on the tested data
sets.

Change-Id: I19ddbcf52a2f01af0ab6dfd7cc25b2e438b9014a
Signed-off-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

show more ...

Merge "refactor(cm): move mpam registers into el2 context" into integration

Merge changes from topic "gr/cpu_ren" into integration

* changes:
chore: rename Blackhawk to Cortex-X925
chore: rename Chaberton to Cortex-A725

chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no long

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.

In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.

Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

show more ...

Merge "fix(imx8m): 8mq: enable imx_hab_handler" into integration

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(cm): move mpam registers into el2 context

* FEAT_MPAM related EL2 registers are placed explicitly outside
the EL2 context in the cpu_context_t structure.

* With EL2 registers now coupled

refactor(cm): move mpam registers into el2 context

* FEAT_MPAM related EL2 registers are placed explicitly outside
the EL2 context in the cpu_context_t structure.

* With EL2 registers now coupled with dependent features, this
patch moves them to the el2_context structure "el2_sysregs_t".

* Further, converting the assembly context-offset entries into a
c structure. It relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.

Change-Id: Ib784bc8d2fbe35a8a47a569426d8663282ec06aa
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

show more ...

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Merge "fix(s32g274a): avoid overwriting const fields" into integration

Merge "feat(mt8188): update SVP region ID and permission" into integration

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2

show more ...

Merge changes I710d1780,Ia9a59bde into integration

* changes:
feat(gpt): configure memory size protected by bitlock
feat(gpt): add support for large GPT mappings

Merge "feat(mt8188): update the memory usage for SCP core0 and core1" into integration

feat(mt8188): update SVP region ID and permission

- Update SVP EMI-MPU region ID from 4 to 5 for resolving
the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain

feat(mt8188): update SVP region ID and permission

- Update SVP EMI-MPU region ID from 4 to 5 for resolving
the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain 1 and domain 6 APC from
FORBIDDEN to SEC_RW.
- Correct the calculation for the end address of SVP DRAM region.
- Add region 0 and region 1 for BL31 and BL32 memory protection.
- Add clear region protection API for SVP region.

Change-Id: Iaea348ad9be629e8a81cf579b148c6df66015b42
Signed-off-by: Haohao Sun <haohao.sun@mediatek.corp-partner.google.com>

show more ...

feat(mt8188): update the memory usage for SCP core0 and core1

- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.

Change-Id: I35547e2ac

feat(mt8188): update the memory usage for SCP core0 and core1

- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.

Change-Id: I35547e2ac928945c244883d2333f921ce578bbd1
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

show more ...

feat(stm32mp15): remove OP-TEE shared mem

The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-

feat(stm32mp15): remove OP-TEE shared mem

The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc

show more ...

Merge "docs(changelog): changelog for v2.11 release" into integration