1 /* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat, mask) \ 16 ((unsigned int)(((reg) >> (feat)) & mask)) 17 18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 19 __attribute__((always_inline)) \ 20 static inline bool is_ ## name ## _supported(void) \ 21 { \ 22 if ((guard) == FEAT_STATE_DISABLED) { \ 23 return false; \ 24 } \ 25 if ((guard) == FEAT_STATE_ALWAYS) { \ 26 return true; \ 27 } \ 28 return read_func(); \ 29 } 30 31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 32 __attribute__((always_inline)) \ 33 static inline bool is_ ## name ## _present(void) \ 34 { \ 35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 36 ? true : false; \ 37 } 38 39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ 40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 41 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 42 43 44 /* +----------------------------+ 45 * | Features supported | 46 * +----------------------------+ 47 * | GENTIMER | 48 * +----------------------------+ 49 * | FEAT_PAN | 50 * +----------------------------+ 51 * | FEAT_VHE | 52 * +----------------------------+ 53 * | FEAT_TTCNP | 54 * +----------------------------+ 55 * | FEAT_UAO | 56 * +----------------------------+ 57 * | FEAT_PACQARMA3 | 58 * +----------------------------+ 59 * | FEAT_PAUTH | 60 * +----------------------------+ 61 * | FEAT_TTST | 62 * +----------------------------+ 63 * | FEAT_BTI | 64 * +----------------------------+ 65 * | FEAT_MTE2 | 66 * +----------------------------+ 67 * | FEAT_SSBS | 68 * +----------------------------+ 69 * | FEAT_NMI | 70 * +----------------------------+ 71 * | FEAT_GCS | 72 * +----------------------------+ 73 * | FEAT_EBEP | 74 * +----------------------------+ 75 * | FEAT_SEBEP | 76 * +----------------------------+ 77 * | FEAT_SEL2 | 78 * +----------------------------+ 79 * | FEAT_TWED | 80 * +----------------------------+ 81 * | FEAT_FGT | 82 * +----------------------------+ 83 * | FEAT_EC/ECV2 | 84 * +----------------------------+ 85 * | FEAT_RNG | 86 * +----------------------------+ 87 * | FEAT_TCR2 | 88 * +----------------------------+ 89 * | FEAT_S2POE | 90 * +----------------------------+ 91 * | FEAT_S1POE | 92 * +----------------------------+ 93 * | FEAT_S2PIE | 94 * +----------------------------+ 95 * | FEAT_S1PIE | 96 * +----------------------------+ 97 * | FEAT_AMU/AMUV1P1 | 98 * +----------------------------+ 99 * | FEAT_MPAM | 100 * +----------------------------+ 101 * | FEAT_HCX | 102 * +----------------------------+ 103 * | FEAT_RNG_TRAP | 104 * +----------------------------+ 105 * | FEAT_RME | 106 * +----------------------------+ 107 * | FEAT_SB | 108 * +----------------------------+ 109 * | FEAT_CSV2/CSV3 | 110 * +----------------------------+ 111 * | FEAT_SPE | 112 * +----------------------------+ 113 * | FEAT_SVE | 114 * +----------------------------+ 115 * | FEAT_RAS | 116 * +----------------------------+ 117 * | FEAT_DIT | 118 * +----------------------------+ 119 * | FEAT_SYS_REG_TRACE | 120 * +----------------------------+ 121 * | FEAT_TRF | 122 * +----------------------------+ 123 * | FEAT_NV/NV2 | 124 * +----------------------------+ 125 * | FEAT_BRBE | 126 * +----------------------------+ 127 * | FEAT_TRBE | 128 * +----------------------------+ 129 * | FEAT_SME/SME2 | 130 * +----------------------------+ 131 * | FEAT_PMUV3 | 132 * +----------------------------+ 133 * | FEAT_MTPMU | 134 * +----------------------------+ 135 */ 136 137 __attribute__((always_inline)) 138 static inline bool is_armv7_gentimer_present(void) 139 { 140 /* The Generic Timer is always present in an ARMv8-A implementation */ 141 return true; 142 } 143 144 /* FEAT_PAN: Privileged access never */ 145 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 146 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN) 147 148 /* FEAT_VHE: Virtualization Host Extensions */ 149 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 150 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE) 151 152 /* FEAT_TTCNP: Translation table common not private */ 153 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 154 ID_AA64MMFR2_EL1_CNP_MASK, 1U) 155 156 /* FEAT_UAO: User access override */ 157 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 158 ID_AA64MMFR2_EL1_UAO_MASK, 1U) 159 160 /* If any of the fields is not zero, QARMA3 algorithm is present */ 161 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 162 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 163 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U) 164 165 /* PAUTH */ 166 __attribute__((always_inline)) 167 static inline bool is_armv8_3_pauth_present(void) 168 { 169 uint64_t mask_id_aa64isar1 = 170 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 171 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 172 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 173 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 174 175 /* 176 * If any of the fields is not zero or QARMA3 is present, 177 * PAuth is present 178 */ 179 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 180 is_feat_pacqarma3_present()); 181 } 182 183 /* FEAT_TTST: Small translation tables */ 184 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 185 ID_AA64MMFR2_EL1_ST_MASK, 1U) 186 187 /* FEAT_BTI: Branch target identification */ 188 CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 189 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED) 190 191 /* FEAT_MTE2: Memory tagging extension */ 192 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 193 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2) 194 195 /* FEAT_SSBS: Speculative store bypass safe */ 196 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 197 ID_AA64PFR1_EL1_SSBS_MASK, 1U) 198 199 /* FEAT_NMI: Non-maskable interrupts */ 200 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 201 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED) 202 203 /* FEAT_EBEP */ 204 CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 205 ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED) 206 207 /* FEAT_SEBEP */ 208 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 209 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED) 210 211 /* FEAT_SEL2: Secure EL2 */ 212 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 213 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2) 214 215 /* FEAT_TWED: Delayed trapping of WFE */ 216 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 217 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED) 218 219 /* FEAT_FGT: Fine-grained traps */ 220 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 221 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT) 222 223 /* FEAT_ECV: Enhanced Counter Virtualization */ 224 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 225 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV) 226 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 227 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) 228 229 /* FEAT_RNG: Random number generator */ 230 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 231 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG) 232 233 /* FEAT_TCR2: Support TCR2_ELx regs */ 234 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 235 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2) 236 237 /* FEAT_S2POE */ 238 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 239 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE) 240 241 /* FEAT_S1POE */ 242 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 243 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE) 244 245 __attribute__((always_inline)) 246 static inline bool is_feat_sxpoe_supported(void) 247 { 248 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 249 } 250 251 /* FEAT_S2PIE */ 252 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 253 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE) 254 255 /* FEAT_S1PIE */ 256 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 257 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE) 258 259 __attribute__((always_inline)) 260 static inline bool is_feat_sxpie_supported(void) 261 { 262 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 263 } 264 265 /* FEAT_GCS: Guarded Control Stack */ 266 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 267 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS) 268 269 /* FEAT_AMU: Activity Monitors Extension */ 270 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 271 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU) 272 273 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 274 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 275 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) 276 277 /* 278 * Return MPAM version: 279 * 280 * 0x00: None Armv8.0 or later 281 * 0x01: v0.1 Armv8.4 or later 282 * 0x10: v1.0 Armv8.2 or later 283 * 0x11: v1.1 Armv8.4 or later 284 * 285 */ 286 __attribute__((always_inline)) 287 static inline bool is_feat_mpam_present(void) 288 { 289 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 290 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 291 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 292 & ID_AA64PFR1_MPAM_FRAC_MASK)); 293 return ret; 294 } 295 296 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 297 298 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 299 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 300 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX) 301 302 /* FEAT_RNG_TRAP: Trapping support */ 303 CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 304 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED) 305 306 /* Return the RME version, zero if not supported. */ 307 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT, 308 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME) 309 310 /* FEAT_SB: Speculation barrier instruction */ 311 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 312 ID_AA64ISAR1_SB_MASK, 1U) 313 314 /* 315 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 316 * of id_aa64pfr0_el1 register and can be used to check for below features: 317 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 318 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 319 * 0b0000 - Feature FEAT_CSV2 is not implemented. 320 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 321 * are not implemented. 322 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 323 * implemented. 324 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 325 */ 326 327 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 328 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) 329 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 330 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) 331 332 /* FEAT_SPE: Statistical Profiling Extension */ 333 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 334 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS) 335 336 /* FEAT_SVE: Scalable Vector Extension */ 337 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 338 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS) 339 340 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 341 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 342 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS) 343 344 /* FEAT_DIT: Data Independent Timing instructions */ 345 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 346 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT) 347 348 /* FEAT_SYS_REG_TRACE */ 349 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT, 350 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS) 351 352 /* FEAT_TRF: TraceFilter */ 353 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 354 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS) 355 356 /* FEAT_NV2: Enhanced Nested Virtualization */ 357 CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 358 ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U) 359 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 360 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) 361 362 /* FEAT_BRBE: Branch Record Buffer Extension */ 363 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 364 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS) 365 366 /* FEAT_TRBE: Trace Buffer Extension */ 367 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 368 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS) 369 370 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 371 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 372 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U) 373 374 /* FEAT_SMEx: Scalar Matrix Extension */ 375 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 376 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS) 377 378 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 379 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) 380 381 /******************************************************************************* 382 * Function to get hardware granularity support 383 ******************************************************************************/ 384 385 __attribute__((always_inline)) 386 static inline bool is_feat_tgran4K_present(void) 387 { 388 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 389 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 390 return (tgranx < 8U); 391 } 392 393 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 394 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED) 395 396 __attribute__((always_inline)) 397 static inline bool is_feat_tgran64K_present(void) 398 { 399 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 400 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 401 return (tgranx < 8U); 402 } 403 404 /* FEAT_PMUV3 */ 405 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 406 ID_AA64DFR0_PMUVER_MASK, 1U) 407 408 /* FEAT_MTPMU */ 409 __attribute__((always_inline)) 410 static inline bool is_feat_mtpmu_present(void) 411 { 412 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 413 ID_AA64DFR0_MTPMU_MASK); 414 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 415 } 416 417 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 418 419 #endif /* ARCH_FEATURES_H */ 420