feat(dt-bindings): new RCC DT bindings

RCC bindings alignment with MP13 RCC bindings:
- merge of 'st,clksrc' and 'st,pkcs' nodes into 'st,clksrc'
- no ordering requirements on 'st,clksrc' node
- use

feat(dt-bindings): new RCC DT bindings

RCC bindings alignment with MP13 RCC bindings:
- merge of 'st,clksrc' and 'st,pkcs' nodes into 'st,clksrc'
- no ordering requirements on 'st,clksrc' node
- use DIV() macro for 'st,clkdiv' node
- no ordering requirements on 'st,clkdiv' node
- new pll binding

Change-Id: Id3ca30608dde2091145123512c42c6958a378d91
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PM

feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PMIC before and after applying clock tree,
always boot at 650MHz, which is the frequency for nominal voltage.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id05a3ee17e7dd57e2d64dc06f8f1e7f9cb21e110

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refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13

Remove useless LSEDRV_MEDIUM_HIGH definition in clk-stm32mp13.c.
It's already defined in include/dt-bindings/clock/stm32mp13-clksrc.h.

Si

refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13

Remove useless LSEDRV_MEDIUM_HIGH definition in clk-stm32mp13.c.
It's already defined in include/dt-bindings/clock/stm32mp13-clksrc.h.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ie3fa4711930f922fa0733ba7c76d72ec9639e9a5

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fix(st-clock): display proper PLL number for STM32MP13

The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by cha

fix(st-clock): display proper PLL number for STM32MP13

The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by changing pll->clk_id in messages with pll->clk_id - _CK_PLL1 + 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic09195ae6fe5f8d3a87e69962425f7c826f3670b

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fix(st-clock): do not reconfigure LSE

If LSE oscillator is already ON, which is the case when returning from
low-power state or if we are on VBAT, it mustn't be reconfigured.

Signed-off-by: Yann Ga

fix(st-clock): do not reconfigure LSE

If LSE oscillator is already ON, which is the case when returning from
low-power state or if we are on VBAT, it mustn't be reconfigured.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie75f2b0b42aeb3d95e2266e1fca811a2f2b3e29f

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feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation

LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG

feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation

LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee

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refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6ca72723eac3e133f1ca0dee504ef344c72e0bf

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refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config

Update function stm32mp_stgen_config() to support deactivated STGEN
when frequency is 0, for example on STOP2 exit for STM32MP25

refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config

Update function stm32mp_stgen_config() to support deactivated STGEN
when frequency is 0, for example on STOP2 exit for STM32MP25.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id371c4602a614bbfa0ecc7ce2d2e0ac5261e1d52

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feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but gene

feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but generic timer
has been reset.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I6f91dbd051f76383e9ff1d6bb86225d373dbf33a

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Merge "fix(allwinner): remove unneeded header inclusion" into integration

Merge changes from topic "mb/refactor-cot" into integration

* changes:
refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file
refactor(auth): remove HW_CONFIG reference from BL1 CoT fi

Merge changes from topic "mb/refactor-cot" into integration

* changes:
refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file
refactor(auth): remove HW_CONFIG reference from BL1 CoT file

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Merge "refactor(fdts): remove unused nodes from CoT device tree" into integration

fix(allwinner): remove unneeded header inclusion

Nothing in sunxi_bl31_setup.c uses any functionality provided by the
fdt_wrappers file, so remove its inclusion from the header list.

Change-Id: I47

fix(allwinner): remove unneeded header inclusion

Nothing in sunxi_bl31_setup.c uses any functionality provided by the
fdt_wrappers file, so remove its inclusion from the header list.

Change-Id: I47031a58add2f85e757e75d8578f4e8e21ef65ea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(imx): disable DRAM retention by default on i.MX8MQ" into integration

Merge changes from topic "xlnx_fix_cpu_pwrdwn_handling" into integration

* changes:
fix(xilinx): handle power down event if SGI not registered
fix(xilinx): register for idle callback

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(rockchip): add RK3566/RK3568 Socs support" into integration

feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
ho

feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
hooks to measure and record firmware image measurements.

Additionally, add support for measured boot at BL1 and BL2 boot stages
on RD-Fremont platforms. The patch adds the RSE measured boot metadata
that includes firmware image IDs, measurement slot number and other
information. It also initializes the AP communication with RSE over
AP-RSE root MHUv3 channel to pass firmware image measurements to RSE to
support extended measurements.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ia1b0bf673e865b31862cb8af79c4c71a5ba4dbea

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feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_F

feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_FW_NVCOUNTER when the caller requests the CCA NV counter.
This allows the platforms to use the CCA CoT on FVP platforms.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ifab724fae63857056b3eeb44eeefc15c4c610eed

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feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id0cfd82ef79598cd8368ba017c145bf34d502e65

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feat(psa): introduce generic library for CCA attestation

Add a generic Arm CCA attestation library driver to interface with the
PSA delegated attestation partition APIs that use RSE to fetch the
pla

feat(psa): introduce generic library for CCA attestation

Add a generic Arm CCA attestation library driver to interface with the
PSA delegated attestation partition APIs that use RSE to fetch the
platform attestation token and Realm attestation key.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I882273e97567cc068f90d2ef089410f3a93c6b00

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feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup

feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup stage.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id79bcdb2fda6cdf394f4e02f67d1c1a44d5ddf23

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feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed

feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic390517a8810df195a2582793b81afdbff5ffa15

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fix(rse): include lib-psa to resolve build

Unless platforms include lib/psa into platform specific makefile the
rse_comms throws build error on its own:
CC drivers/arm/rse/rse_comms_protocol.

fix(rse): include lib-psa to resolve build

Unless platforms include lib/psa into platform specific makefile the
rse_comms throws build error on its own:
CC drivers/arm/rse/rse_comms_protocol.c
drivers/arm/rse/rse_comms.c:13:10: fatal error: psa/client.h: No such file or directory
13 | #include <psa/client.h>

So add PLAT_INCLUDES entry to include the lib/psa to rse_comms.mk.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I4cbcbbaf20285990239d605f0b3b3dc92bea61e6

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feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design

feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ie4ebf47a10f2f6e33c7ecfc8008e30bacc62bf3d

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