Merge "fix(cm): remove set_aapcs_args functions" into integration

Merge "fix(cpufeat): enable FEAT_FGWTE3 after FEAT_CPA" into integration

fix(cpus): fix C1 Pro powerdown abandon behavior

This change restores a toggle to IMP_CPUPWRCTLR_EL1.CORE_PWRDN_EN
that was accidentally changed to a bitset in [1]. Without this change, a
powerdown

fix(cpus): fix C1 Pro powerdown abandon behavior

This change restores a toggle to IMP_CPUPWRCTLR_EL1.CORE_PWRDN_EN
that was accidentally changed to a bitset in [1]. Without this change, a
powerdown abandon followed by a non-powerdown CPU_SUSPEND will
incorrectly trigger a power down.

This change is similar to [2].

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/42920/
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43236/

Change-Id: Ife86bd2b5bac4829e695a1aa180926dfad19a470
Signed-off-by: Jim Ray <jimray@google.com>

show more ...

fix(cpufeat): enable FEAT_FGWTE3 after FEAT_CPA

FEAT_CPA needs to write SCTLR2_EL3 which will be forbidden after
initialising FEAT_FGWTE3. Correct the order.

Change-Id: I3a0554d2a73f773b3ad672eb1e4

fix(cpufeat): enable FEAT_FGWTE3 after FEAT_CPA

FEAT_CPA needs to write SCTLR2_EL3 which will be forbidden after
initialising FEAT_FGWTE3. Correct the order.

Change-Id: I3a0554d2a73f773b3ad672eb1e4b0db0171d38bd
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor(cm): reduce conditional compilation

Context debug needs to switch between EL1 and EL2 context but it can
re-use its variables and function calls with a bit of clever naming.
Unify them to r

refactor(cm): reduce conditional compilation

Context debug needs to switch between EL1 and EL2 context but it can
re-use its variables and function calls with a bit of clever naming.
Unify them to reduce #if-s.

Change-Id: I401667c4bc07938c99163c035dbed1101d986859
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(cm): remove set_aapcs_args functions

These functions were added as wrappers on context but were never used,
mainly because we sometimes only have a reference to the gpregs
sub-struct. Remove the

fix(cm): remove set_aapcs_args functions

These functions were added as wrappers on context but were never used,
mainly because we sometimes only have a reference to the gpregs
sub-struct. Remove them to reduce clutter.

Change-Id: If10dade6ea9cc90384344cf0149482574cf0e116
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's

fix(psci): gate suspend end_pwrlvl override in OS_INIT mode at runtime

This change adds an additional runtime gate to override the
suspend power level. The build-time check already existed, but
it's possible that PSCI might not be in OS_INIT mode. In that
case, no override should occur.

Change-Id: I695cef3f4ddd8957360fe056c8715c170df6f1f4
Signed-off-by: Bill Peckham <bpeckham@google.com>
Signed-off-by: Karunatharaka Bodduluri <karunatharaka@google.com>

show more ...

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
docs(security): update CVE-2024-7881 affected CPU revisions
fix(security): update Neoverse-V2 fix version for CVE-2024-7

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
docs(security): update CVE-2024-7881 affected CPU revisions
fix(security): update Neoverse-V2 fix version for CVE-2024-7881
fix(security): update Cortex-X3 fix version for CVE-2024-7881
fix(security): update Neoverse-V3/V3AE fix version for CVE-2024-7881
fix(security): update Cortex-X925 fix version for CVE-2024-7881
fix(security): update Cortex-X4 fix version for CVE-2024-7881

show more ...

docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse

docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse-V3 [5] and Neoverse-V3AE [6].
Errata IDs for reference in the respective SDENs

Cortex-X3 - 3692984
Cortex-X4 - 3692983
Cortex-X925 - 3692980
Neoverse-V2 - 3696445
Neoverse-V3/V3AE - 3696307

[1] https://developer.arm.com/documentation/SDEN-2055130/latest/
[2] https://developer.arm.com/documentation/SDEN-2432808/latest
[3] https://developer.arm.com/documentation/109180/latest/
[4] https://developer.arm.com/documentation/SDEN-2332927/latest
[5] https://developer.arm.com/documentation/SDEN-2891958/latest/
[6] https://developer.arm.com/documentation/SDEN-2615521/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iad109561a144169fd3805c179a4f8e3bfdd59a65

show more ...

fix(security): update Neoverse-V2 fix version for CVE-2024-7881

This patch updates the Neoverse-V2 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696445 [2] applies.
The erratum applies

fix(security): update Neoverse-V2 fix version for CVE-2024-7881

This patch updates the Neoverse-V2 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696445 [2] applies.
The erratum applies to r0p0, r0p1, r0p2 and is still open.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1ae196fa8ce4579524faba4916f631e7c4db358b

show more ...

fix(security): update Cortex-X3 fix version for CVE-2024-7881

This patch updates the Cortex-X3 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3692984 [2] applies.
The erratum applies to r

fix(security): update Cortex-X3 fix version for CVE-2024-7881

This patch updates the Cortex-X3 revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3692984 [2] applies.
The erratum applies to r0p0, r1p0, r1p1, r1p2 and is still open.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2055130/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1ff75602a0dfa758a223549d92ea87543fa44b6

show more ...

docs(maintainers): add Gabriel as clock framework maintainer

Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.

Change-Id: I7af885

docs(maintainers): add Gabriel as clock framework maintainer

Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.

Change-Id: I7af8857def86b8042b9ddd3709f4888df51f6544
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

docs(maintainers): sort frameworks alphabetically

Sort the "Drivers, Libraries and Framework Code" chapter alphabetically.

Change-Id: I7fc84d2c72085851514dcc9aa65825bffc7eba39
Signed-off-by: Yann G

docs(maintainers): sort frameworks alphabetically

Sort the "Drivers, Libraries and Framework Code" chapter alphabetically.

Change-Id: I7fc84d2c72085851514dcc9aa65825bffc7eba39
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

fix(security): update Neoverse-V3/V3AE fix version for CVE-2024-7881

This patch updates the Neoverse-V3 / Neoverse-V3AE revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696307 [2][3] appli

fix(security): update Neoverse-V3/V3AE fix version for CVE-2024-7881

This patch updates the Neoverse-V3 / Neoverse-V3AE revisions for
which the CVE-2024-7881 [1] / Cat B erratum 3696307 [2][3] applies.
The erratum applies to r0p0, r0p1 and is fixed in r0p2.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2891958/latest/
[3] https://developer.arm.com/documentation/SDEN-2615521/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If3e2989a4b5a5c68dc12e23978b226c73f21ba14

show more ...

Merge "feat(fvp): load SP_PKGs with TRANSFER_LIST" into integration

fix(psci): set requested local power states in failure path

In OS initiated coordination, it's possible that the platform
function pwr_domain_validate_suspend may return a non-success
value. In that

fix(psci): set requested local power states in failure path

In OS initiated coordination, it's possible that the platform
function pwr_domain_validate_suspend may return a non-success
value. In that case, PSCI must set the
psci_req_local_pwr_states values to run.

Change-Id: I2c94af024935ab156c806b90a7094c40e1667fb7
Signed-off-by: Bill Peckham <bpeckham@google.com>
Signed-off-by: Karunatharaka Bodduluri <karunatharaka@google.com>

show more ...

fix(security): update Cortex-X925 fix version for CVE-2024-7881

This patch updates the Cortex-X925 revisions for which the
CVE-2024-7881 [1] / Cat B erratum 3692980 [2] applies. The erratum
applies

fix(security): update Cortex-X925 fix version for CVE-2024-7881

This patch updates the Cortex-X925 revisions for which the
CVE-2024-7881 [1] / Cat B erratum 3692980 [2] applies. The erratum
applies to r0p0, r0p1 and is fixed in r0p2.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/109180/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice7a939bed60d44cff5706a08b2b59d6777760b0

show more ...

fix(security): update Cortex-X4 fix version for CVE-2024-7881

This patch updates the Cortex-X4 revisions for which the
CVE-2024-7881 [1] / Cat B erratum 3692983 [2] applies. The erratum
applies to r

fix(security): update Cortex-X4 fix version for CVE-2024-7881

This patch updates the Cortex-X4 revisions for which the
CVE-2024-7881 [1] / Cat B erratum 3692983 [2] applies. The erratum
applies to r0p0, r0p1, r0p2 and is fixed in r0p3.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iae84f26fdce96a61fdc942b7595ccf8b9c7783f9

show more ...

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
docs(security): update CVE-2024-7881 affected CPUs list
fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU
fi

Merge changes from topic "ar/smccc_arch_wa_4" into integration

* changes:
docs(security): update CVE-2024-7881 affected CPUs list
fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU
fix(security): add CVE-2024-7881 mitigation to C1-Pro CPU
fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU
docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

show more ...

Merge "fix(cm): do not check for AArch32 support to enable features" into integration

Merge "fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes" into integration

docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash

docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia2cc39d0f91bab89a911e271cf83c788d71bb85c

show more ...

fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

T

fix(security): add CVE-2024-7881 mitigation to C1-Ultra CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Ultra CPU. This CVE applies to r0p0 and is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111077/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I7815d6fc9af812c38b1c05881c850b8209d6ad7c

show more ...

fix(security): add CVE-2024-7881 mitigation to C1-Pro CPU

This patch mitigates Cat B erratum 3684268 [2] / CVE-2024-7881 [1]
for C1-Pro CPU. This CVE applies to r0p0, r1p0 and
is fixed in r1p1 [2].

fix(security): add CVE-2024-7881 mitigation to C1-Pro CPU

This patch mitigates Cat B erratum 3684268 [2] / CVE-2024-7881 [1]
for C1-Pro CPU. This CVE applies to r0p0, r1p0 and
is fixed in r1p1 [2].

This CVE can be mitigated by disabling the affected prefetcher
by setting IMP_CPUECTLR_EL1[49].

Note: C1-Pro has a different workaround for CVE-2024-7881
which is not reflected in Security Bulletin yet. Refer
SDEN for correct workaround description.

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-3273080/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6b0eca1fc340f18dcbede920a0dd1c882bfe12c1

show more ...

fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2]

fix(security): add CVE-2024-7881 mitigation to C1-Premium CPU

This patch mitigates Cat B erratum 3651221 [2] / CVE-2024-7881 [1]
for C1-Premium CPU. This CVE applies to r0p0 and
is fixed in r1p0 [2].

This CVE can be mitigated by disabling the affected prefetcher
setting CPUACTLR6_EL1[41].

[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/111078/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I70b50700bc1618e0f8f4121efc9fe89e2742ed74

show more ...