feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc

feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc_rgm_release_part`
to make use of `mc_rgm_release_periph` function.

Change-Id: Ia2e049ac461f823379ddce34b1406eea0a0a86e9
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): rem

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): remove CVE_2022_23960 Cortex-A720

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feat(cpus): enable Maximum Power Mitigation Mechanism

Add Maximum Power Mitigation Mechanism(MPMM) for Veymont and Caddo
CPUs.

Change-Id: I4beedd9b95e0fe4069d9cfbf8c0211ccbcaf7f90
Signed-off-by: Go

feat(cpus): enable Maximum Power Mitigation Mechanism

Add Maximum Power Mitigation Mechanism(MPMM) for Veymont and Caddo
CPUs.

Change-Id: I4beedd9b95e0fe4069d9cfbf8c0211ccbcaf7f90
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(arm): derive RMM bank size from payload" into integration

Merge "fix(rmmd): correct activation condition check" into integration

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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Merge "refactor(docs): deduplicate PSCI documentation" into integration

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Cortex-X4

Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://d

fix(security): remove CVE_2022_23960 Cortex-X4

Cortex-X4 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102484/0003/The-Cortex-X4--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-X4 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@8c87becbc64f2e233ac905aa006d5e15a63a9a8b

Change-Id: I23f5fa748377a920340b3c5a6584ccfadeea901a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102530/0002/The-Cortex-A720--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-A720 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I3c68b5f5d85ede37a6a039369de8ed2aa9205395
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for venom cpu

Add basic CPU library code to support Venom CPU

Change-Id: I84d4cb77b175812811a17e55b4b290585e05d216
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite

refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite lots going on around PSCI so it's clearly not read often.
The only part that isn't is that for describing a new secure dispatcher,
which belongs in the porting guide.

Change-Id: Icdc53e19565f0785bc8a112e5eb49df1b365c66c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(build): update GCC toolchain requirement to 14.3.Rel1" into integration

fix(dsu): dsu config for all cores in hot reset

This allows DSU units to be configured across all cpu clusters
instead of the primary cluster. This configures actlr_el3 in the
hot reset path to allo

fix(dsu): dsu config for all cores in hot reset

This allows DSU units to be configured across all cpu clusters
instead of the primary cluster. This configures actlr_el3 in the
hot reset path to allow power control and PMU registers for all
cores in lower ELs and fixes.

Change-Id: If4dd254736fbcc4bcb8785a16972a0132bc477ce
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL33 will
load directly after BL31.

Revised the ARM_GPT_SUPPORT description to note that it must be
enabled when the FIP image resides in a GPT partition on Secure Flash.

Change-Id: I79905efd026994290d0bc6c07cdf1f5a903c9194
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specif

feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specified, and removes a redundant entry for BL31
in platform definitions for mmap entries aswell.

Change-Id: I6a3ec97c8f41d6bddc4f20b6edc088a46e2caa75
Signed-off-by: Archish Venkatesh <Archish.Venkatesh@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "feat(scmi): add support for discovering and changing parent clocks" into integration

Merge "feat(cpus): add support for Dionysus cpu library" into integration

feat(scmi): add support for discovering and changing parent clocks

Add base support for discovering and changing parent clocks

This is the part of SCMI platform design document version 3.2,
which i

feat(scmi): add support for discovering and changing parent clocks

Add base support for discovering and changing parent clocks

This is the part of SCMI platform design document version 3.2,
which introduces SCMI clock protocol version 3.0

Add mandatory support for CLOCK_CONFIG_GET which is needed
for SCMI clock protocol version 3.0

Also, add support for clock_enable_delay parameter which got
introduced as new parameter in return values for command
CLOCK_ATTRIBUTES in same SCMI Platform design document v3.2

Change-Id: Ie5cba83dad27bf1e3b51c11c0218259a44c1af59
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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chore(compiler-rt): update compiler-rt to v21.1.4

Source: https://github.com/llvm/llvm-project/tree/llvmorg-21.1.4
Change-Id: Ic2ebfb7770a3b88f2c294b31262504c9cb90f48d
Signed-off-by: Chris Kay <chri

chore(compiler-rt): update compiler-rt to v21.1.4

Source: https://github.com/llvm/llvm-project/tree/llvmorg-21.1.4
Change-Id: Ic2ebfb7770a3b88f2c294b31262504c9cb90f48d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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chore(zlib): update zlib to v1.3.1

Source: https://github.com/madler/zlib/tree/v1.3.1
Change-Id: I2ab8c7449aef1ad6e95b14a0f690d394d47e1088
Signed-off-by: Chris Kay <chris.kay@arm.com>

chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A reposit

chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A repository. Doing so reduces the manual overhead of
updating libfdt in the future, as we avoid the need to analyse
individual source-level dependencies.

libfdt, conveniently, also provides a Makefile designed to ease its
integration into foreign build systems (like TF-A's), which we also make
use of in this change.

Source: https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/?h=v1.7.2
Change-Id: I8babcfd27019fdd6d255d550491e1bb733745f27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(maintainers): update QTI platform maintainers

Add myself to the list of QTI platform maintainers.

Change-Id: I779f457cf075bf42acb62b75223912d7b4f1e95b
Signed-off-by: Sumit Garg <sumit.garg@oss

docs(maintainers): update QTI platform maintainers

Add myself to the list of QTI platform maintainers.

Change-Id: I779f457cf075bf42acb62b75223912d7b4f1e95b
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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