1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <stdbool.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <arch_features.h>
17 #include <bl31/interrupt_mgmt.h>
18 #include <common/bl_common.h>
19 #include <common/debug.h>
20 #include <context.h>
21 #include <drivers/arm/gicv3.h>
22 #include <lib/cpus/cpu_ops.h>
23 #include <lib/cpus/errata.h>
24 #include <lib/el3_runtime/context_mgmt.h>
25 #include <lib/el3_runtime/cpu_data.h>
26 #include <lib/el3_runtime/pubsub_events.h>
27 #include <lib/extensions/amu.h>
28 #include <lib/extensions/brbe.h>
29 #include <lib/extensions/cpa2.h>
30 #include <lib/extensions/debug_v8p9.h>
31 #include <lib/extensions/fgt2.h>
32 #include <lib/extensions/idte3.h>
33 #include <lib/extensions/mpam.h>
34 #include <lib/extensions/pauth.h>
35 #include <lib/extensions/pmuv3.h>
36 #include <lib/extensions/sme.h>
37 #include <lib/extensions/spe.h>
38 #include <lib/extensions/sve.h>
39 #include <lib/extensions/sysreg128.h>
40 #include <lib/extensions/sys_reg_trace.h>
41 #include <lib/extensions/tcr2.h>
42 #include <lib/extensions/trbe.h>
43 #include <lib/extensions/trf.h>
44 #include <lib/utils.h>
45
46 #if ENABLE_FEAT_TWED
47 /* Make sure delay value fits within the range(0-15) */
48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
49 #endif /* ENABLE_FEAT_TWED */
50
51 per_world_context_t per_world_context[CPU_CONTEXT_NUM];
52
53 static void manage_extensions_nonsecure(cpu_context_t *ctx);
54 static void manage_extensions_secure(cpu_context_t *ctx);
55
56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
setup_el1_context(cpu_context_t * ctx,const struct entry_point_info * ep)57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
58 {
59 u_register_t sctlr_elx, actlr_elx;
60
61 /*
62 * Initialise SCTLR_EL1 to the reset value corresponding to the target
63 * execution state setting all fields rather than relying on the hw.
64 * Some fields have architecturally UNKNOWN reset values and these are
65 * set to zero.
66 *
67 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
68 *
69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
70 * required by PSCI specification)
71 */
72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
73 if (GET_RW(ep->spsr) == MODE_RW_64) {
74 sctlr_elx |= SCTLR_EL1_RES1;
75 } else {
76 /*
77 * If the target execution state is AArch32 then the following
78 * fields need to be set.
79 *
80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
81 * instructions are not trapped to EL1.
82 *
83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
84 * instructions are not trapped to EL1.
85 *
86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
87 * CP15DMB, CP15DSB, and CP15ISB instructions.
88 */
89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
91 }
92
93 /*
94 * If workaround of errata 764081 for Cortex-A75 is used then set
95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
96 */
97 if (errata_a75_764081_applies()) {
98 sctlr_elx |= SCTLR_IESB_BIT;
99 }
100
101 /* Store the initialised SCTLR_EL1 value in the cpu_context */
102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
103
104 /*
105 * Base the context ACTLR_EL1 on the current value, as it is
106 * implementation defined. The context restore process will write
107 * the value from the context to the actual register and can cause
108 * problems for processor cores that don't expect certain bits to
109 * be zero.
110 */
111 actlr_elx = read_actlr_el1();
112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx);
113 }
114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */
115
116 /******************************************************************************
117 * This function performs initializations that are specific to SECURE state
118 * and updates the cpu context specified by 'ctx'.
119 *****************************************************************************/
setup_secure_context(cpu_context_t * ctx,const struct entry_point_info * ep)120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
121 {
122 u_register_t scr_el3;
123 el3_state_t *state;
124
125 state = get_el3state_ctx(ctx);
126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
127
128 #if defined(IMAGE_BL31) && !defined(SPD_spmd)
129 /*
130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
131 * indicated by the interrupt routing model for BL31.
132 */
133 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
134 #endif
135
136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
137 if (is_feat_mte2_supported()) {
138 scr_el3 |= SCR_ATA_BIT;
139 }
140
141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
142
143 /*
144 * Initialize EL1 context registers unless SPMC is running
145 * at S-EL2.
146 */
147 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1
148 setup_el1_context(ctx, ep);
149 #endif
150
151 manage_extensions_secure(ctx);
152 }
153
154 #if ENABLE_RME && IMAGE_BL31
155 /******************************************************************************
156 * This function performs initializations that are specific to REALM state
157 * and updates the cpu context specified by 'ctx'.
158 *
159 * NOTE: any changes to this function must be verified by an RMMD maintainer.
160 *****************************************************************************/
setup_realm_context(cpu_context_t * ctx,const struct entry_point_info * ep)161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
162 {
163 u_register_t scr_el3;
164 el3_state_t *state;
165 el2_sysregs_t *el2_ctx;
166
167 state = get_el3state_ctx(ctx);
168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
169 el2_ctx = get_el2_sysregs_ctx(ctx);
170
171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
172
173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM);
174
175 /* CSV2 version 2 and above */
176 if (is_feat_csv2_2_supported()) {
177 /* Enable access to the SCXTNUM_ELx registers. */
178 scr_el3 |= SCR_EnSCXT_BIT;
179 }
180
181 if (is_feat_sctlr2_supported()) {
182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to
183 * SCTLR2_ELx registers.
184 */
185 scr_el3 |= SCR_SCTLR2En_BIT;
186 }
187
188 if (is_feat_d128_supported()) {
189 /*
190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit
191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
193 */
194 scr_el3 |= SCR_D128En_BIT;
195 }
196
197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
198
199 if (is_feat_fgt2_supported()) {
200 fgt2_enable(ctx);
201 }
202
203 if (is_feat_debugv8p9_supported()) {
204 debugv8p9_extended_bp_wp_enable(ctx);
205 }
206
207 if (is_feat_brbe_supported()) {
208 brbe_enable(ctx);
209 }
210
211 /*
212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world.
213 */
214 if (is_feat_sme_supported()) {
215 sme_enable(ctx);
216 }
217
218 if (is_feat_spe_supported()) {
219 spe_disable_realm(ctx);
220 }
221
222 if (is_feat_trbe_supported()) {
223 trbe_disable_realm(ctx);
224 }
225 }
226 #endif /* ENABLE_RME && IMAGE_BL31 */
227
228 /******************************************************************************
229 * This function performs initializations that are specific to NON-SECURE state
230 * and updates the cpu context specified by 'ctx'.
231 *****************************************************************************/
setup_ns_context(cpu_context_t * ctx,const struct entry_point_info * ep)232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
233 {
234 u_register_t scr_el3;
235 el3_state_t *state;
236
237 state = get_el3state_ctx(ctx);
238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
239
240 /* SCR_NS: Set the NS bit */
241 scr_el3 |= SCR_NS_BIT;
242
243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
244 if (is_feat_mte2_supported()) {
245 scr_el3 |= SCR_ATA_BIT;
246 }
247
248 /*
249 * Pointer Authentication feature, if present, is always enabled by
250 * default for Non secure lower exception levels. We do not have an
251 * explicit flag to set it. To prevent the leakage between the worlds
252 * during world switch, we enable it only for the non-secure world.
253 *
254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
255 * exception levels of secure and realm worlds.
256 *
257 * If the Secure/realm world wants to use pointer authentication,
258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
259 * it will be enabled globally for all the contexts.
260 *
261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
262 * other than EL3
263 *
264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
265 * than EL3
266 */
267 if (!is_ctx_pauth_supported()) {
268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
269 }
270
271 #if HANDLE_EA_EL3_FIRST_NS
272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
273 scr_el3 |= SCR_EA_BIT;
274 #endif
275
276 #if RAS_TRAP_NS_ERR_REC_ACCESS
277 /*
278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
279 * and RAS ERX registers from EL1 and EL2(from any security state)
280 * are trapped to EL3.
281 * Set here to trap only for NS EL1/EL2
282 */
283 scr_el3 |= SCR_TERR_BIT;
284 #endif
285
286 /* CSV2 version 2 and above */
287 if (is_feat_csv2_2_supported()) {
288 /* Enable access to the SCXTNUM_ELx registers. */
289 scr_el3 |= SCR_EnSCXT_BIT;
290 }
291
292 #ifdef IMAGE_BL31
293 /*
294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
295 * indicated by the interrupt routing model for BL31.
296 */
297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
298 #endif
299
300 if (is_feat_the_supported()) {
301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to
302 * RCWMASK_EL1 and RCWSMASK_EL1 registers.
303 */
304 scr_el3 |= SCR_RCWMASKEn_BIT;
305 }
306
307 if (is_feat_sctlr2_supported()) {
308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to
309 * SCTLR2_ELx registers.
310 */
311 scr_el3 |= SCR_SCTLR2En_BIT;
312 }
313
314 if (is_feat_d128_supported()) {
315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit
316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
318 */
319 scr_el3 |= SCR_D128En_BIT;
320 }
321
322 if (is_feat_fpmr_supported()) {
323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR
324 * register.
325 */
326 scr_el3 |= SCR_EnFPM_BIT;
327 }
328
329 if (is_feat_aie_supported()) {
330 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2
331 * system registers from NS world.
332 */
333 scr_el3 |= SCR_AIEn_BIT;
334 }
335
336 if (is_feat_pfar_supported()) {
337 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR
338 * system registers from NS world.
339 */
340 scr_el3 |= SCR_PFAREn_BIT;
341 }
342
343 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
344
345 /* Initialize EL2 context registers */
346 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
347 if (is_feat_hcx_supported()) {
348 /*
349 * Initialize register HCRX_EL2 with its init value.
350 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
351 * chance that this can lead to unexpected behavior in lower
352 * ELs that have not been updated since the introduction of
353 * this feature if not properly initialized, especially when
354 * it comes to those bits that enable/disable traps.
355 */
356 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2,
357 HCRX_EL2_INIT_VAL);
358 }
359
360 if (is_feat_fgt_supported()) {
361 /*
362 * Initialize HFG*_EL2 registers with a default value so legacy
363 * systems unaware of FEAT_FGT do not get trapped due to their lack
364 * of initialization for this feature.
365 */
366 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2,
367 HFGITR_EL2_INIT_VAL);
368 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2,
369 HFGRTR_EL2_INIT_VAL);
370 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2,
371 HFGWTR_EL2_INIT_VAL);
372 }
373 #else
374 /* Initialize EL1 context registers */
375 setup_el1_context(ctx, ep);
376 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
377
378 manage_extensions_nonsecure(ctx);
379 }
380
381 /*******************************************************************************
382 * The following function performs initialization of the cpu_context 'ctx'
383 * for first use that is common to all security states, and sets the
384 * initial entrypoint state as specified by the entry_point_info structure.
385 *
386 * The EE and ST attributes are used to configure the endianness and secure
387 * timer availability for the new execution context.
388 ******************************************************************************/
setup_context_common(cpu_context_t * ctx,const entry_point_info_t * ep)389 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
390 {
391 u_register_t scr_el3;
392 u_register_t mdcr_el3;
393 el3_state_t *state;
394 gp_regs_t *gp_regs;
395
396 state = get_el3state_ctx(ctx);
397
398 /* Clear any residual register values from the context */
399 zeromem(ctx, sizeof(*ctx));
400
401 /*
402 * The lower-EL context is zeroed so that no stale values leak to a world.
403 * It is assumed that an all-zero lower-EL context is good enough for it
404 * to boot correctly. However, there are very few registers where this
405 * is not true and some values need to be recreated.
406 */
407 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
408 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx);
409
410 /*
411 * These bits are set in the gicv3 driver. Losing them (especially the
412 * SRE bit) is problematic for all worlds. Henceforth recreate them.
413 */
414 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
415 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
416 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
417
418 /*
419 * The actlr_el2 register can be initialized in platform's reset handler
420 * and it may contain access control bits (e.g. CLUSTERPMUEN bit).
421 */
422 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2());
423 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
424
425 /* Start with a clean SCR_EL3 copy as all relevant values are set */
426 scr_el3 = SCR_RESET_VAL;
427
428 /*
429 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
430 * EL2, EL1 and EL0 are not trapped to EL3.
431 *
432 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
433 * EL2, EL1 and EL0 are not trapped to EL3.
434 *
435 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
436 * both Security states and both Execution states.
437 *
438 * SCR_EL3.SIF: Set to one to disable secure instruction execution from
439 * Non-secure memory.
440 */
441 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT);
442
443 scr_el3 |= SCR_SIF_BIT;
444
445 /*
446 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
447 * Exception level as specified by SPSR.
448 */
449 if (GET_RW(ep->spsr) == MODE_RW_64) {
450 scr_el3 |= SCR_RW_BIT;
451 }
452
453 /*
454 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
455 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
456 * next mode is Hyp.
457 */
458 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
459 || ((GET_RW(ep->spsr) != MODE_RW_64)
460 && (GET_M32(ep->spsr) == MODE32_hyp))) {
461 scr_el3 |= SCR_HCE_BIT;
462 }
463
464 /*
465 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
466 * Secure timer registers to EL3, from AArch64 state only, if specified
467 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
468 * bit always behaves as 1 (i.e. secure physical timer register access
469 * is not trapped)
470 */
471 if (EP_GET_ST(ep->h.attr) != 0U) {
472 scr_el3 |= SCR_ST_BIT;
473 }
474
475 /*
476 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
477 * SCR_EL3.HXEn.
478 */
479 if (is_feat_hcx_supported()) {
480 scr_el3 |= SCR_HXEn_BIT;
481 }
482
483 /*
484 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by
485 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting
486 * SCR_EL3.EnAS0.
487 */
488 if (is_feat_ls64_accdata_supported()) {
489 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT;
490 }
491
492 /*
493 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
494 * registers are trapped to EL3.
495 */
496 if (is_feat_rng_trap_supported()) {
497 scr_el3 |= SCR_TRNDR_BIT;
498 }
499
500 #if FAULT_INJECTION_SUPPORT
501 /* Enable fault injection from lower ELs */
502 scr_el3 |= SCR_FIEN_BIT;
503 #endif
504
505 /*
506 * Enable Pointer Authentication globally for all the worlds.
507 *
508 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
509 * other than EL3
510 *
511 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
512 * than EL3
513 */
514 if (is_ctx_pauth_supported()) {
515 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
516 }
517
518 /*
519 * SCR_EL3.PIEN: Enable permission indirection and overlay
520 * registers for AArch64 if present.
521 */
522 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) {
523 scr_el3 |= SCR_PIEN_BIT;
524 }
525
526 /* SCR_EL3.GCSEn: Enable GCS registers. */
527 if (is_feat_gcs_supported()) {
528 scr_el3 |= SCR_GCSEn_BIT;
529 }
530
531 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */
532 if (is_feat_fgt_supported()) {
533 scr_el3 |= SCR_FGTEN_BIT;
534 }
535
536 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */
537 if (is_feat_ecv_supported()) {
538 scr_el3 |= SCR_ECVEN_BIT;
539 }
540
541 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
542 if (is_feat_twed_supported()) {
543 /* Set delay in SCR_EL3 */
544 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
545 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
546 << SCR_TWEDEL_SHIFT);
547
548 /* Enable WFE delay */
549 scr_el3 |= SCR_TWEDEn_BIT;
550 }
551
552 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
553 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */
554 if (is_feat_sel2_supported()) {
555 scr_el3 |= SCR_EEL2_BIT;
556 }
557 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
558
559 if (is_feat_mec_supported()) {
560 scr_el3 |= SCR_MECEn_BIT;
561 }
562
563 /*
564 * Populate EL3 state so that we've the right context
565 * before doing ERET
566 */
567 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
568 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
569 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
570
571 /* Start with a clean MDCR_EL3 copy as all relevant values are set */
572 mdcr_el3 = MDCR_EL3_RESET_VAL;
573
574 /* ---------------------------------------------------------------------
575 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
576 * Some fields are architecturally UNKNOWN on reset.
577 *
578 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
579 * Debug exceptions, other than Breakpoint Instruction exceptions, are
580 * disabled from all ELs in Secure state.
581 *
582 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
583 * privileged debug from S-EL1.
584 *
585 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
586 * access to the powerdown debug registers do not trap to EL3.
587 *
588 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
589 * debug registers, other than those registers that are controlled by
590 * MDCR_EL3.TDOSA.
591 */
592 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
593 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ;
594 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3);
595
596 #if IMAGE_BL31
597 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */
598 if (is_feat_trf_supported()) {
599 trf_enable(ctx);
600 }
601
602 if (is_feat_tcr2_supported()) {
603 tcr2_enable(ctx);
604 }
605
606 pmuv3_enable(ctx);
607
608 if (is_feat_idte3_supported()) {
609 idte3_enable(ctx);
610 }
611
612 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31
613 /*
614 * Initialize SCTLR_EL2 context register with reset value.
615 */
616 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
617 #endif /* CTX_INCLUDE_EL2_REGS */
618 #endif /* IMAGE_BL31 */
619
620 /*
621 * Store the X0-X7 value from the entrypoint into the context
622 * Use memcpy as we are in control of the layout of the structures
623 */
624 gp_regs = get_gpregs_ctx(ctx);
625 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
626 }
627
628 /*******************************************************************************
629 * Context management library initialization routine. This library is used by
630 * runtime services to share pointers to 'cpu_context' structures for secure
631 * non-secure and realm states. Management of the structures and their associated
632 * memory is not done by the context management library e.g. the PSCI service
633 * manages the cpu context used for entry from and exit to the non-secure state.
634 * The Secure payload dispatcher service manages the context(s) corresponding to
635 * the secure state. It also uses this library to get access to the non-secure
636 * state cpu context pointers.
637 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
638 * which will be used for programming an entry into a lower EL. The same context
639 * will be used to save state upon exception entry from that EL.
640 ******************************************************************************/
cm_init(void)641 void __init cm_init(void)
642 {
643 /*
644 * The context management library has only global data to initialize, but
645 * that will be done when the BSS is zeroed out.
646 */
647 }
648
649 /*******************************************************************************
650 * This is the high-level function used to initialize the cpu_context 'ctx' for
651 * first use. It performs initializations that are common to all security states
652 * and initializations specific to the security state specified in 'ep'
653 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)654 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
655 {
656 size_t security_state;
657
658 assert(ctx != NULL);
659
660 /*
661 * Perform initializations that are common
662 * to all security states
663 */
664 setup_context_common(ctx, ep);
665
666 security_state = GET_SECURITY_STATE(ep->h.attr);
667
668 /* Perform security state specific initializations */
669 switch (security_state) {
670 case SECURE:
671 setup_secure_context(ctx, ep);
672 break;
673 #if ENABLE_RME && IMAGE_BL31
674 case REALM:
675 setup_realm_context(ctx, ep);
676 break;
677 #endif
678 case NON_SECURE:
679 setup_ns_context(ctx, ep);
680 break;
681 default:
682 ERROR("Invalid security state\n");
683 panic();
684 break;
685 }
686 }
687
688 /*******************************************************************************
689 * Enable architecture extensions for EL3 execution. This function only updates
690 * registers in-place which are expected to either never change or be
691 * overwritten by el3_exit. Expects the core_pos of the current core as argument.
692 ******************************************************************************/
cm_manage_extensions_el3(unsigned int my_idx)693 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx)
694 {
695 if (is_feat_pauth_supported()) {
696 pauth_init_enable_el3();
697 }
698
699 #if IMAGE_BL31
700 if (is_feat_sve_supported()) {
701 sve_init_el3();
702 }
703
704 if (is_feat_amu_supported()) {
705 amu_init_el3(my_idx);
706 }
707
708 if (is_feat_sme_supported()) {
709 sme_init_el3();
710 }
711
712 if (is_feat_mpam_supported()) {
713 mpam_init_el3();
714 }
715
716 if (is_feat_cpa2_supported()) {
717 cpa2_enable_el3();
718 }
719
720 pmuv3_init_el3();
721
722 /* NOTE: must be done last, makes the configuration immutable */
723 if (is_feat_fgwte3_supported()) {
724 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL);
725 }
726 #endif /* IMAGE_BL31 */
727 }
728
729 /******************************************************************************
730 * Function to initialise the registers with the RESET values in the context
731 * memory, which are maintained per world.
732 ******************************************************************************/
cm_el3_arch_init_per_world(per_world_context_t * per_world_ctx)733 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
734 {
735 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL;
736 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
737 }
738
739 /*******************************************************************************
740 * Initialise per_world_context for Non-Secure world.
741 * This function enables the architecture extensions, which have same value
742 * across the cores for the non-secure world.
743 ******************************************************************************/
manage_extensions_nonsecure_per_world(void)744 static void manage_extensions_nonsecure_per_world(void)
745 {
746 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
747
748 #if IMAGE_BL31
749 if (is_feat_sme_supported()) {
750 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
751 }
752
753 if (is_feat_sve_supported()) {
754 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
755 }
756
757 if (is_feat_amu_supported()) {
758 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
759 }
760
761 if (is_feat_sys_reg_trace_supported()) {
762 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
763 }
764
765 if (is_feat_mpam_supported()) {
766 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
767 }
768
769 if (is_feat_idte3_supported()) {
770 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS);
771 }
772 #endif /* IMAGE_BL31 */
773 }
774
775 /*******************************************************************************
776 * Initialise per_world_context for Secure world.
777 * This function enables the architecture extensions, which have same value
778 * across the cores for the secure world.
779 ******************************************************************************/
manage_extensions_secure_per_world(void)780 static void manage_extensions_secure_per_world(void)
781 {
782 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
783
784 #if IMAGE_BL31
785 if (is_feat_sme_supported()) {
786
787 if (ENABLE_SME_FOR_SWD) {
788 /*
789 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
790 * SME, SVE, and FPU/SIMD context properly managed.
791 */
792 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
793 } else {
794 /*
795 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
796 * world can safely use the associated registers.
797 */
798 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
799 }
800 }
801 if (is_feat_sve_supported()) {
802 if (ENABLE_SVE_FOR_SWD) {
803 /*
804 * Enable SVE and FPU in secure context, SPM must ensure
805 * that the SVE and FPU register contexts are properly managed.
806 */
807 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
808 } else {
809 /*
810 * Disable SVE and FPU in secure context so non-secure world
811 * can safely use them.
812 */
813 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
814 }
815 }
816
817 /* NS can access this but Secure shouldn't */
818 if (is_feat_sys_reg_trace_supported()) {
819 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
820 }
821
822 if (is_feat_idte3_supported()) {
823 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE);
824 }
825 #endif /* IMAGE_BL31 */
826 }
827
manage_extensions_realm_per_world(void)828 static void manage_extensions_realm_per_world(void)
829 {
830 #if ENABLE_RME && IMAGE_BL31
831 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]);
832
833 if (is_feat_sve_supported()) {
834 /*
835 * Enable SVE and FPU in realm context when it is enabled for NS.
836 * Realm manager must ensure that the SVE and FPU register
837 * contexts are properly managed.
838 */
839 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
840 }
841
842 /* NS can access this but Realm shouldn't */
843 if (is_feat_sys_reg_trace_supported()) {
844 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
845 }
846
847 /*
848 * If SME/SME2 is supported and enabled for NS world, then disable trapping
849 * of SME instructions for Realm world. RMM will save/restore required
850 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE.
851 */
852 if (is_feat_sme_supported()) {
853 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
854 }
855
856 /*
857 * If FEAT_MPAM is supported and enabled, then disable trapping access
858 * to the MPAM registers for Realm world. Instead, RMM will configure
859 * the access to be trapped by itself so it can inject undefined aborts
860 * back to the Realm.
861 */
862 if (is_feat_mpam_supported()) {
863 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
864 }
865
866 if (is_feat_idte3_supported()) {
867 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM);
868 }
869 #endif /* ENABLE_RME && IMAGE_BL31 */
870 }
871
cm_manage_extensions_per_world(void)872 void cm_manage_extensions_per_world(void)
873 {
874 manage_extensions_nonsecure_per_world();
875 manage_extensions_secure_per_world();
876 manage_extensions_realm_per_world();
877 }
878
cm_init_percpu_once_regs(void)879 void cm_init_percpu_once_regs(void)
880 {
881 #if IMAGE_BL31
882 if (is_feat_idte3_supported()) {
883 idte3_init_percpu_once_regs(CPU_CONTEXT_NS);
884 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE);
885 #if ENABLE_RME
886 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM);
887 #endif /* ENABLE_RME */
888 }
889 #endif /* IMAGE_BL31 */
890 }
891
892 /*******************************************************************************
893 * Enable architecture extensions on first entry to Non-secure world.
894 ******************************************************************************/
manage_extensions_nonsecure(cpu_context_t * ctx)895 static void manage_extensions_nonsecure(cpu_context_t *ctx)
896 {
897 #if IMAGE_BL31
898 /* NOTE: registers are not context switched */
899 if (is_feat_amu_supported()) {
900 amu_enable(ctx);
901 }
902
903 if (is_feat_sme_supported()) {
904 sme_enable(ctx);
905 }
906
907 if (is_feat_fgt2_supported()) {
908 fgt2_enable(ctx);
909 }
910
911 if (is_feat_debugv8p9_supported()) {
912 debugv8p9_extended_bp_wp_enable(ctx);
913 }
914
915 if (is_feat_spe_supported()) {
916 spe_enable_ns(ctx);
917 }
918
919 if (is_feat_trbe_supported()) {
920 if (check_if_trbe_disable_affected_core()) {
921 trbe_disable_ns(ctx);
922 } else {
923 trbe_enable_ns(ctx);
924 }
925 }
926
927 if (is_feat_brbe_supported()) {
928 brbe_enable(ctx);
929 }
930 #endif /* IMAGE_BL31 */
931 }
932
933 #if INIT_UNUSED_NS_EL2
934 /*******************************************************************************
935 * Enable architecture extensions in-place at EL2 on first entry to Non-secure
936 * world when EL2 is empty and unused.
937 ******************************************************************************/
manage_extensions_nonsecure_el2_unused(void)938 static void manage_extensions_nonsecure_el2_unused(void)
939 {
940 #if IMAGE_BL31
941 if (is_feat_spe_supported()) {
942 spe_init_el2_unused();
943 }
944
945 if (is_feat_amu_supported()) {
946 amu_init_el2_unused();
947 }
948
949 if (is_feat_mpam_supported()) {
950 mpam_init_el2_unused();
951 }
952
953 if (is_feat_trbe_supported()) {
954 trbe_init_el2_unused();
955 }
956
957 if (is_feat_sys_reg_trace_supported()) {
958 sys_reg_trace_init_el2_unused();
959 }
960
961 if (is_feat_trf_supported()) {
962 trf_init_el2_unused();
963 }
964
965 pmuv3_init_el2_unused();
966
967 if (is_feat_sve_supported()) {
968 sve_init_el2_unused();
969 }
970
971 if (is_feat_sme_supported()) {
972 sme_init_el2_unused();
973 }
974
975 if (is_feat_mops_supported() && is_feat_hcx_supported()) {
976 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT);
977 }
978
979 if (is_feat_pauth_supported()) {
980 pauth_enable_el2();
981 }
982 #endif /* IMAGE_BL31 */
983 }
984 #endif /* INIT_UNUSED_NS_EL2 */
985
986 /*******************************************************************************
987 * Enable architecture extensions on first entry to Secure world.
988 ******************************************************************************/
manage_extensions_secure(cpu_context_t * ctx)989 static void manage_extensions_secure(cpu_context_t *ctx)
990 {
991 #if IMAGE_BL31
992 if (is_feat_sme_supported()) {
993 if (ENABLE_SME_FOR_SWD) {
994 /*
995 * Enable SME, SVE, FPU/SIMD in secure context, secure manager
996 * must ensure SME, SVE, and FPU/SIMD context properly managed.
997 */
998 sme_init_el3();
999 sme_enable(ctx);
1000 } else {
1001 /*
1002 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
1003 * world can safely use the associated registers.
1004 */
1005 sme_disable(ctx);
1006 }
1007 }
1008
1009 if (is_feat_spe_supported()) {
1010 spe_disable_secure(ctx);
1011 }
1012
1013 if (is_feat_trbe_supported()) {
1014 trbe_disable_secure(ctx);
1015 }
1016 #endif /* IMAGE_BL31 */
1017 }
1018
1019 /*******************************************************************************
1020 * The following function initializes the cpu_context for the current CPU
1021 * for first use, and sets the initial entrypoint state as specified by the
1022 * entry_point_info structure.
1023 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)1024 void cm_init_my_context(const entry_point_info_t *ep)
1025 {
1026 cpu_context_t *ctx;
1027 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
1028 cm_setup_context(ctx, ep);
1029 }
1030
1031 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
init_nonsecure_el2_unused(cpu_context_t * ctx)1032 static void init_nonsecure_el2_unused(cpu_context_t *ctx)
1033 {
1034 #if INIT_UNUSED_NS_EL2
1035 u_register_t hcr_el2 = HCR_RESET_VAL;
1036 u_register_t mdcr_el2;
1037 u_register_t scr_el3;
1038
1039 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1040
1041 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
1042 if ((scr_el3 & SCR_RW_BIT) != 0U) {
1043 hcr_el2 |= HCR_RW_BIT;
1044 }
1045
1046 write_hcr_el2(hcr_el2);
1047
1048 /*
1049 * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
1050 * All fields have architecturally UNKNOWN reset values.
1051 */
1052 write_cptr_el2(CPTR_EL2_RESET_VAL);
1053
1054 /*
1055 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
1056 * reset and are set to zero except for field(s) listed below.
1057 *
1058 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
1059 * Non-secure EL0 and EL1 accesses to the physical timer registers.
1060 *
1061 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
1062 * Non-secure EL0 and EL1 accesses to the physical counter registers.
1063 */
1064 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
1065
1066 /*
1067 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
1068 * UNKNOWN value.
1069 */
1070 write_cntvoff_el2(0);
1071
1072 /*
1073 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
1074 * respectively.
1075 */
1076 write_vpidr_el2(read_midr_el1());
1077 write_vmpidr_el2(read_mpidr_el1());
1078
1079 /*
1080 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
1081 *
1082 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
1083 * translation is disabled, cache maintenance operations depend on the
1084 * VMID.
1085 *
1086 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
1087 * disabled.
1088 */
1089 write_vttbr_el2(VTTBR_RESET_VAL &
1090 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
1091 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
1092
1093 /*
1094 * Initialise MDCR_EL2, setting all fields rather than relying on hw.
1095 * Some fields are architecturally UNKNOWN on reset.
1096 *
1097 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
1098 * register accesses to the Debug ROM registers are not trapped to EL2.
1099 *
1100 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
1101 * accesses to the powerdown debug registers are not trapped to EL2.
1102 *
1103 * MDCR_EL2.TDA: Set to zero so that System register accesses to the
1104 * debug registers do not trap to EL2.
1105 *
1106 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
1107 * EL2.
1108 */
1109 mdcr_el2 = MDCR_EL2_RESET_VAL &
1110 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
1111 MDCR_EL2_TDE_BIT);
1112
1113 write_mdcr_el2(mdcr_el2);
1114
1115 /*
1116 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
1117 *
1118 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
1119 * EL1 accesses to System registers do not trap to EL2.
1120 */
1121 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
1122
1123 /*
1124 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
1125 * reset.
1126 *
1127 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
1128 * and prevent timer interrupts.
1129 */
1130 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
1131
1132 manage_extensions_nonsecure_el2_unused();
1133 #endif /* INIT_UNUSED_NS_EL2 */
1134 }
1135
1136 /*******************************************************************************
1137 * Prepare the CPU system registers for first entry into realm, secure, or
1138 * normal world.
1139 *
1140 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
1141 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
1142 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
1143 * For all entries, the EL1 registers are initialized from the cpu_context
1144 ******************************************************************************/
cm_prepare_el3_exit(size_t security_state)1145 void cm_prepare_el3_exit(size_t security_state)
1146 {
1147 u_register_t sctlr_el2, scr_el3;
1148 cpu_context_t *ctx = cm_get_context(security_state);
1149
1150 assert(ctx != NULL);
1151
1152 if (security_state == NON_SECURE) {
1153 uint64_t el2_implemented = el_implemented(2);
1154
1155 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
1156 CTX_SCR_EL3);
1157
1158 if (el2_implemented != EL_IMPL_NONE) {
1159
1160 /*
1161 * If context is not being used for EL2, initialize
1162 * HCRX_EL2 with its init value here.
1163 */
1164 if (is_feat_hcx_supported()) {
1165 write_hcrx_el2(HCRX_EL2_INIT_VAL);
1166 }
1167
1168 /*
1169 * Initialize Fine-grained trap registers introduced
1170 * by FEAT_FGT so all traps are initially disabled when
1171 * switching to EL2 or a lower EL, preventing undesired
1172 * behavior.
1173 */
1174 if (is_feat_fgt_supported()) {
1175 /*
1176 * Initialize HFG*_EL2 registers with a default
1177 * value so legacy systems unaware of FEAT_FGT
1178 * do not get trapped due to their lack of
1179 * initialization for this feature.
1180 */
1181 write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
1182 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
1183 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
1184 }
1185
1186 /* Condition to ensure EL2 is being used. */
1187 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
1188 /* Initialize SCTLR_EL2 register with reset value. */
1189 sctlr_el2 = SCTLR_EL2_RES1;
1190
1191 /*
1192 * If workaround of errata 764081 for Cortex-A75
1193 * is used then set SCTLR_EL2.IESB to enable
1194 * Implicit Error Synchronization Barrier.
1195 */
1196 if (errata_a75_764081_applies()) {
1197 sctlr_el2 |= SCTLR_IESB_BIT;
1198 }
1199
1200 write_sctlr_el2(sctlr_el2);
1201 } else {
1202 /*
1203 * (scr_el3 & SCR_HCE_BIT==0)
1204 * EL2 implemented but unused.
1205 */
1206 init_nonsecure_el2_unused(ctx);
1207 }
1208 }
1209
1210 if (is_feat_fgwte3_supported()) {
1211 /*
1212 * TCR_EL3 and ACTLR_EL3 could be overwritten
1213 * by platforms and hence is locked a bit late.
1214 */
1215 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL);
1216 }
1217 }
1218 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1
1219 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */
1220 cm_el1_sysregs_context_restore(security_state);
1221 #endif
1222 cm_set_next_eret_context(security_state);
1223 }
1224
1225 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
1226
el2_sysregs_context_save_fgt(el2_sysregs_t * ctx)1227 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
1228 {
1229 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2());
1230 if (is_feat_amu_supported()) {
1231 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2());
1232 }
1233 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2());
1234 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2());
1235 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2());
1236 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2());
1237 }
1238
el2_sysregs_context_restore_fgt(el2_sysregs_t * ctx)1239 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
1240 {
1241 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2));
1242 if (is_feat_amu_supported()) {
1243 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2));
1244 }
1245 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2));
1246 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2));
1247 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2));
1248 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2));
1249 }
1250
el2_sysregs_context_save_fgt2(el2_sysregs_t * ctx)1251 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx)
1252 {
1253 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2());
1254 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2());
1255 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2());
1256 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2());
1257 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2());
1258 }
1259
el2_sysregs_context_restore_fgt2(el2_sysregs_t * ctx)1260 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx)
1261 {
1262 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2));
1263 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2));
1264 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2));
1265 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2));
1266 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2));
1267 }
1268
el2_sysregs_context_save_mpam(el2_sysregs_t * ctx)1269 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx)
1270 {
1271 u_register_t mpam_idr = read_mpamidr_el1();
1272
1273 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2());
1274
1275 /*
1276 * The context registers that we intend to save would be part of the
1277 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1.
1278 */
1279 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1280 return;
1281 }
1282
1283 /*
1284 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if
1285 * MPAMIDR_HAS_HCR_BIT == 1.
1286 */
1287 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2());
1288 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2());
1289 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2());
1290
1291 /*
1292 * The number of MPAMVPM registers is implementation defined, their
1293 * number is stored in the MPAMIDR_EL1 register.
1294 */
1295 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1296 case 7:
1297 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2());
1298 __fallthrough;
1299 case 6:
1300 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2());
1301 __fallthrough;
1302 case 5:
1303 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2());
1304 __fallthrough;
1305 case 4:
1306 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2());
1307 __fallthrough;
1308 case 3:
1309 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2());
1310 __fallthrough;
1311 case 2:
1312 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2());
1313 __fallthrough;
1314 case 1:
1315 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2());
1316 break;
1317 }
1318 }
1319
el2_sysregs_context_restore_mpam(el2_sysregs_t * ctx)1320 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx)
1321 {
1322 u_register_t mpam_idr = read_mpamidr_el1();
1323
1324 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2));
1325
1326 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1327 return;
1328 }
1329
1330 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2));
1331 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2));
1332 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2));
1333
1334 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1335 case 7:
1336 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2));
1337 __fallthrough;
1338 case 6:
1339 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2));
1340 __fallthrough;
1341 case 5:
1342 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2));
1343 __fallthrough;
1344 case 4:
1345 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2));
1346 __fallthrough;
1347 case 3:
1348 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2));
1349 __fallthrough;
1350 case 2:
1351 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2));
1352 __fallthrough;
1353 case 1:
1354 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2));
1355 break;
1356 }
1357 }
1358
1359 /* ---------------------------------------------------------------------------
1360 * The following registers are not added:
1361 * ICH_AP0R<n>_EL2
1362 * ICH_AP1R<n>_EL2
1363 * ICH_LR<n>_EL2
1364 *
1365 * NOTE: For a system with S-EL2 present but not enabled, accessing
1366 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the
1367 * SCR_EL3.NS = 1 before accessing this register.
1368 * ---------------------------------------------------------------------------
1369 */
el2_sysregs_context_save_gic(el2_sysregs_t * ctx,uint32_t security_state)1370 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state)
1371 {
1372 u_register_t scr_el3 = read_scr_el3();
1373
1374 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1375 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1376 #else
1377 write_scr_el3(scr_el3 | SCR_NS_BIT);
1378 isb();
1379
1380 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1381
1382 write_scr_el3(scr_el3);
1383 isb();
1384 #endif
1385 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2());
1386
1387 if (errata_ich_vmcr_el2_applies()) {
1388 if (security_state == SECURE) {
1389 write_scr_el3(scr_el3 & ~SCR_NS_BIT);
1390 } else {
1391 write_scr_el3(scr_el3 | SCR_NS_BIT);
1392 }
1393 isb();
1394 }
1395
1396 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2());
1397
1398 if (errata_ich_vmcr_el2_applies()) {
1399 write_scr_el3(scr_el3);
1400 isb();
1401 }
1402 }
1403
el2_sysregs_context_restore_gic(el2_sysregs_t * ctx,uint32_t security_state)1404 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state)
1405 {
1406 u_register_t scr_el3 = read_scr_el3();
1407
1408 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1409 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1410 #else
1411 write_scr_el3(scr_el3 | SCR_NS_BIT);
1412 isb();
1413
1414 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1415
1416 write_scr_el3(scr_el3);
1417 isb();
1418 #endif
1419 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2));
1420
1421 if (errata_ich_vmcr_el2_applies()) {
1422 if (security_state == SECURE) {
1423 write_scr_el3(scr_el3 & ~SCR_NS_BIT);
1424 } else {
1425 write_scr_el3(scr_el3 | SCR_NS_BIT);
1426 }
1427 isb();
1428 }
1429
1430 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2));
1431
1432 if (errata_ich_vmcr_el2_applies()) {
1433 write_scr_el3(scr_el3);
1434 isb();
1435 }
1436 }
1437
1438 /* -----------------------------------------------------
1439 * The following registers are not added:
1440 * AMEVCNTVOFF0<n>_EL2
1441 * AMEVCNTVOFF1<n>_EL2
1442 * -----------------------------------------------------
1443 */
el2_sysregs_context_save_common(el2_sysregs_t * ctx)1444 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
1445 {
1446 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2());
1447 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2());
1448 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2());
1449 write_el2_ctx_common(ctx, amair_el2, read_amair_el2());
1450 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2());
1451 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2());
1452 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2());
1453 if (CTX_INCLUDE_AARCH32_REGS) {
1454 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2());
1455 }
1456 write_el2_ctx_common(ctx, elr_el2, read_elr_el2());
1457 write_el2_ctx_common(ctx, esr_el2, read_esr_el2());
1458 write_el2_ctx_common(ctx, far_el2, read_far_el2());
1459 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2());
1460 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2());
1461 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2());
1462 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2());
1463 write_el2_ctx_common(ctx, mair_el2, read_mair_el2());
1464 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2());
1465 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2());
1466 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2());
1467 write_el2_ctx_common(ctx, sp_el2, read_sp_el2());
1468 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2());
1469 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2());
1470 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2());
1471 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2());
1472 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2());
1473 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2());
1474
1475 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2());
1476 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2());
1477 }
1478
el2_sysregs_context_restore_common(el2_sysregs_t * ctx)1479 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
1480 {
1481 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2));
1482 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2));
1483 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2));
1484 write_amair_el2(read_el2_ctx_common(ctx, amair_el2));
1485 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2));
1486 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2));
1487 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2));
1488 if (CTX_INCLUDE_AARCH32_REGS) {
1489 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2));
1490 }
1491 write_elr_el2(read_el2_ctx_common(ctx, elr_el2));
1492 write_esr_el2(read_el2_ctx_common(ctx, esr_el2));
1493 write_far_el2(read_el2_ctx_common(ctx, far_el2));
1494 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2));
1495 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2));
1496 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2));
1497 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2));
1498 write_mair_el2(read_el2_ctx_common(ctx, mair_el2));
1499 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2));
1500 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2));
1501 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2));
1502 write_sp_el2(read_el2_ctx_common(ctx, sp_el2));
1503 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2));
1504 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2));
1505 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2));
1506 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2));
1507 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2));
1508 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2));
1509 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2));
1510 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2));
1511 }
1512
1513 /*******************************************************************************
1514 * Save EL2 sysreg context
1515 ******************************************************************************/
cm_el2_sysregs_context_save(uint32_t security_state)1516 void cm_el2_sysregs_context_save(uint32_t security_state)
1517 {
1518 cpu_context_t *ctx;
1519 el2_sysregs_t *el2_sysregs_ctx;
1520
1521 ctx = cm_get_context(security_state);
1522 assert(ctx != NULL);
1523
1524 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1525
1526 el2_sysregs_context_save_common(el2_sysregs_ctx);
1527 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state);
1528
1529 if (is_feat_mte2_supported()) {
1530 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
1531 }
1532
1533 if (is_feat_mpam_supported()) {
1534 el2_sysregs_context_save_mpam(el2_sysregs_ctx);
1535 }
1536
1537 if (is_feat_fgt_supported()) {
1538 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
1539 }
1540
1541 if (is_feat_fgt2_supported()) {
1542 el2_sysregs_context_save_fgt2(el2_sysregs_ctx);
1543 }
1544
1545 if (is_feat_ecv_v2_supported()) {
1546 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2());
1547 }
1548
1549 if (is_feat_vhe_supported()) {
1550 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2,
1551 read_contextidr_el2());
1552 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2());
1553 }
1554
1555 if (is_feat_ras_supported()) {
1556 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2());
1557 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2());
1558 }
1559
1560 if (is_feat_nv2_supported()) {
1561 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2());
1562 }
1563
1564 if (is_feat_trf_supported()) {
1565 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2());
1566 }
1567
1568 if (is_feat_csv2_2_supported()) {
1569 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2,
1570 read_scxtnum_el2());
1571 }
1572
1573 if (is_feat_hcx_supported()) {
1574 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2());
1575 }
1576
1577 if (is_feat_tcr2_supported()) {
1578 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2());
1579 }
1580
1581 if (is_feat_s1pie_supported()) {
1582 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2());
1583 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2());
1584 }
1585
1586 if (is_feat_s1poe_supported()) {
1587 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2());
1588 }
1589
1590 if (is_feat_brbe_supported()) {
1591 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2());
1592 }
1593
1594 if (is_feat_s2pie_supported()) {
1595 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2());
1596 }
1597
1598 if (is_feat_gcs_supported()) {
1599 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
1600 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
1601 }
1602
1603 if (is_feat_sctlr2_supported()) {
1604 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2());
1605 }
1606 }
1607
1608 /*******************************************************************************
1609 * Restore EL2 sysreg context
1610 ******************************************************************************/
cm_el2_sysregs_context_restore(uint32_t security_state)1611 void cm_el2_sysregs_context_restore(uint32_t security_state)
1612 {
1613 cpu_context_t *ctx;
1614 el2_sysregs_t *el2_sysregs_ctx;
1615
1616 ctx = cm_get_context(security_state);
1617 assert(ctx != NULL);
1618
1619 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1620
1621 el2_sysregs_context_restore_common(el2_sysregs_ctx);
1622 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state);
1623
1624 if (is_feat_mte2_supported()) {
1625 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2));
1626 }
1627
1628 if (is_feat_mpam_supported()) {
1629 el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
1630 }
1631
1632 if (is_feat_fgt_supported()) {
1633 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
1634 }
1635
1636 if (is_feat_fgt2_supported()) {
1637 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx);
1638 }
1639
1640 if (is_feat_ecv_v2_supported()) {
1641 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2));
1642 }
1643
1644 if (is_feat_vhe_supported()) {
1645 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx,
1646 contextidr_el2));
1647 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2));
1648 }
1649
1650 if (is_feat_ras_supported()) {
1651 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2));
1652 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2));
1653 }
1654
1655 if (is_feat_nv2_supported()) {
1656 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2));
1657 }
1658
1659 if (is_feat_trf_supported()) {
1660 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2));
1661 }
1662
1663 if (is_feat_csv2_2_supported()) {
1664 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx,
1665 scxtnum_el2));
1666 }
1667
1668 if (is_feat_hcx_supported()) {
1669 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2));
1670 }
1671
1672 if (is_feat_tcr2_supported()) {
1673 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2));
1674 }
1675
1676 if (is_feat_s1pie_supported()) {
1677 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2));
1678 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2));
1679 }
1680
1681 if (is_feat_s1poe_supported()) {
1682 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2));
1683 }
1684
1685 if (is_feat_s2pie_supported()) {
1686 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2));
1687 }
1688
1689 if (is_feat_gcs_supported()) {
1690 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
1691 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
1692 }
1693
1694 if (is_feat_sctlr2_supported()) {
1695 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2));
1696 }
1697
1698 if (is_feat_brbe_supported()) {
1699 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2));
1700 }
1701 }
1702 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1703
1704 /*******************************************************************************
1705 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1706 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1707 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1708 * cm_prepare_el3_exit function.
1709 ******************************************************************************/
cm_prepare_el3_exit_ns(void)1710 void cm_prepare_el3_exit_ns(void)
1711 {
1712 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
1713 #if ENABLE_ASSERTIONS
1714 cpu_context_t *ctx = cm_get_context(NON_SECURE);
1715 assert(ctx != NULL);
1716
1717 /* Assert that EL2 is used. */
1718 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1719 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1720 (el_implemented(2U) != EL_IMPL_NONE));
1721 #endif /* ENABLE_ASSERTIONS */
1722
1723 /* Restore EL2 sysreg contexts */
1724 cm_el2_sysregs_context_restore(NON_SECURE);
1725 cm_set_next_eret_context(NON_SECURE);
1726 #else
1727 cm_prepare_el3_exit(NON_SECURE);
1728 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1729 }
1730
1731 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
1732 /*******************************************************************************
1733 * The next set of six functions are used by runtime services to save and restore
1734 * EL1 context on the 'cpu_context' structure for the specified security state.
1735 ******************************************************************************/
el1_sysregs_context_save(el1_sysregs_t * ctx)1736 static void el1_sysregs_context_save(el1_sysregs_t *ctx)
1737 {
1738 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1());
1739 write_el1_ctx_common(ctx, elr_el1, read_elr_el1());
1740
1741 #if (!ERRATA_SPECULATIVE_AT)
1742 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1());
1743 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1());
1744 #endif /* (!ERRATA_SPECULATIVE_AT) */
1745
1746 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1());
1747 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1());
1748 write_el1_ctx_common(ctx, sp_el1, read_sp_el1());
1749 write_el1_ctx_common(ctx, esr_el1, read_esr_el1());
1750 write_el1_ctx_common(ctx, mair_el1, read_mair_el1());
1751 write_el1_ctx_common(ctx, amair_el1, read_amair_el1());
1752 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1());
1753 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1());
1754 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0());
1755 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0());
1756 write_el1_ctx_common(ctx, far_el1, read_far_el1());
1757 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1());
1758 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1());
1759 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1());
1760 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1());
1761 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1());
1762 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1());
1763
1764 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1());
1765 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1());
1766 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1());
1767
1768 if (CTX_INCLUDE_AARCH32_REGS) {
1769 /* Save Aarch32 registers */
1770 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt());
1771 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und());
1772 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq());
1773 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq());
1774 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2());
1775 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2());
1776 }
1777
1778 /* Save counter-timer kernel control register */
1779 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1());
1780 #if NS_TIMER_SWITCH
1781 /* Save NS Timer registers */
1782 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0());
1783 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0());
1784 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0());
1785 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0());
1786 #endif
1787
1788 if (is_feat_mte2_supported()) {
1789 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1());
1790 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1());
1791 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1());
1792 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1());
1793 }
1794
1795 if (is_feat_ras_supported()) {
1796 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1());
1797 }
1798
1799 if (is_feat_s1pie_supported()) {
1800 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1());
1801 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1());
1802 }
1803
1804 if (is_feat_s1poe_supported()) {
1805 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1());
1806 }
1807
1808 if (is_feat_s2poe_supported()) {
1809 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1());
1810 }
1811
1812 if (is_feat_tcr2_supported()) {
1813 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1());
1814 }
1815
1816 if (is_feat_trf_supported()) {
1817 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1());
1818 }
1819
1820 if (is_feat_csv2_2_supported()) {
1821 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0());
1822 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1());
1823 }
1824
1825 if (is_feat_gcs_supported()) {
1826 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1());
1827 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1());
1828 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1());
1829 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0());
1830 }
1831
1832 if (is_feat_the_supported()) {
1833 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1());
1834 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1());
1835 }
1836
1837 if (is_feat_sctlr2_supported()) {
1838 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1());
1839 }
1840
1841 if (is_feat_ls64_accdata_supported()) {
1842 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1());
1843 }
1844 }
1845
el1_sysregs_context_restore(el1_sysregs_t * ctx)1846 static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
1847 {
1848 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1));
1849 write_elr_el1(read_el1_ctx_common(ctx, elr_el1));
1850
1851 #if (!ERRATA_SPECULATIVE_AT)
1852 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1));
1853 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1));
1854 #endif /* (!ERRATA_SPECULATIVE_AT) */
1855
1856 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1));
1857 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1));
1858 write_sp_el1(read_el1_ctx_common(ctx, sp_el1));
1859 write_esr_el1(read_el1_ctx_common(ctx, esr_el1));
1860 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1));
1861 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1));
1862 write_mair_el1(read_el1_ctx_common(ctx, mair_el1));
1863 write_amair_el1(read_el1_ctx_common(ctx, amair_el1));
1864 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1));
1865 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1));
1866 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0));
1867 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0));
1868 write_par_el1(read_el1_ctx_common(ctx, par_el1));
1869 write_far_el1(read_el1_ctx_common(ctx, far_el1));
1870 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1));
1871 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1));
1872 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1));
1873 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1));
1874 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1));
1875 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1));
1876
1877 if (CTX_INCLUDE_AARCH32_REGS) {
1878 /* Restore Aarch32 registers */
1879 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt));
1880 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und));
1881 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq));
1882 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq));
1883 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2));
1884 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2));
1885 }
1886
1887 /* Restore counter-timer kernel control register */
1888 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1));
1889 #if NS_TIMER_SWITCH
1890 /* Restore NS Timer registers */
1891 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0));
1892 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0));
1893 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0));
1894 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0));
1895 #endif
1896
1897 if (is_feat_mte2_supported()) {
1898 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1));
1899 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1));
1900 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1));
1901 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1));
1902 }
1903
1904 if (is_feat_ras_supported()) {
1905 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1));
1906 }
1907
1908 if (is_feat_s1pie_supported()) {
1909 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1));
1910 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1));
1911 }
1912
1913 if (is_feat_s1poe_supported()) {
1914 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1));
1915 }
1916
1917 if (is_feat_s2poe_supported()) {
1918 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1));
1919 }
1920
1921 if (is_feat_tcr2_supported()) {
1922 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1));
1923 }
1924
1925 if (is_feat_trf_supported()) {
1926 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1));
1927 }
1928
1929 if (is_feat_csv2_2_supported()) {
1930 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0));
1931 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1));
1932 }
1933
1934 if (is_feat_gcs_supported()) {
1935 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1));
1936 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1));
1937 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1));
1938 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0));
1939 }
1940
1941 if (is_feat_the_supported()) {
1942 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1));
1943 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1));
1944 }
1945
1946 if (is_feat_sctlr2_supported()) {
1947 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1));
1948 }
1949
1950 if (is_feat_ls64_accdata_supported()) {
1951 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1));
1952 }
1953 }
1954
1955 /*******************************************************************************
1956 * The next couple of functions are used by runtime services to save and restore
1957 * EL1 context on the 'cpu_context' structure for the specified security state.
1958 ******************************************************************************/
cm_el1_sysregs_context_save(uint32_t security_state)1959 void cm_el1_sysregs_context_save(uint32_t security_state)
1960 {
1961 cpu_context_t *ctx;
1962
1963 ctx = cm_get_context(security_state);
1964 assert(ctx != NULL);
1965
1966 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
1967
1968 #if IMAGE_BL31
1969 if (security_state == SECURE) {
1970 PUBLISH_EVENT(cm_exited_secure_world);
1971 } else {
1972 PUBLISH_EVENT(cm_exited_normal_world);
1973 }
1974 #endif
1975 }
1976
cm_el1_sysregs_context_restore(uint32_t security_state)1977 void cm_el1_sysregs_context_restore(uint32_t security_state)
1978 {
1979 cpu_context_t *ctx;
1980
1981 ctx = cm_get_context(security_state);
1982 assert(ctx != NULL);
1983
1984 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
1985
1986 #if IMAGE_BL31
1987 if (security_state == SECURE) {
1988 PUBLISH_EVENT(cm_entering_secure_world);
1989 } else {
1990 PUBLISH_EVENT(cm_entering_normal_world);
1991 }
1992 #endif
1993 }
1994
1995 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */
1996
1997 /*******************************************************************************
1998 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1999 * given security state with the given entrypoint
2000 ******************************************************************************/
cm_set_elr_el3(uint32_t security_state,uintptr_t entrypoint)2001 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
2002 {
2003 cpu_context_t *ctx;
2004 el3_state_t *state;
2005
2006 ctx = cm_get_context(security_state);
2007 assert(ctx != NULL);
2008
2009 /* Populate EL3 state so that ERET jumps to the correct entry */
2010 state = get_el3state_ctx(ctx);
2011 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
2012 }
2013
2014 /*******************************************************************************
2015 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
2016 * pertaining to the given security state
2017 ******************************************************************************/
cm_set_elr_spsr_el3(uint32_t security_state,uintptr_t entrypoint,uint32_t spsr)2018 void cm_set_elr_spsr_el3(uint32_t security_state,
2019 uintptr_t entrypoint, uint32_t spsr)
2020 {
2021 cpu_context_t *ctx;
2022 el3_state_t *state;
2023
2024 ctx = cm_get_context(security_state);
2025 assert(ctx != NULL);
2026
2027 /* Populate EL3 state so that ERET jumps to the correct entry */
2028 state = get_el3state_ctx(ctx);
2029 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
2030 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
2031 }
2032
2033 /*******************************************************************************
2034 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
2035 * pertaining to the given security state using the value and bit position
2036 * specified in the parameters. It preserves all other bits.
2037 ******************************************************************************/
cm_write_scr_el3_bit(uint32_t security_state,uint32_t bit_pos,uint32_t value)2038 void cm_write_scr_el3_bit(uint32_t security_state,
2039 uint32_t bit_pos,
2040 uint32_t value)
2041 {
2042 cpu_context_t *ctx;
2043 el3_state_t *state;
2044 u_register_t scr_el3;
2045
2046 ctx = cm_get_context(security_state);
2047 assert(ctx != NULL);
2048
2049 /* Ensure that the bit position is a valid one */
2050 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
2051
2052 /* Ensure that the 'value' is only a bit wide */
2053 assert(value <= 1U);
2054
2055 /*
2056 * Get the SCR_EL3 value from the cpu context, clear the desired bit
2057 * and set it to its new value.
2058 */
2059 state = get_el3state_ctx(ctx);
2060 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
2061 scr_el3 &= ~(1UL << bit_pos);
2062 scr_el3 |= (u_register_t)value << bit_pos;
2063 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
2064 }
2065
2066 /*******************************************************************************
2067 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
2068 * given security state.
2069 ******************************************************************************/
cm_get_scr_el3(uint32_t security_state)2070 u_register_t cm_get_scr_el3(uint32_t security_state)
2071 {
2072 const cpu_context_t *ctx;
2073 const el3_state_t *state;
2074
2075 ctx = cm_get_context(security_state);
2076 assert(ctx != NULL);
2077
2078 /* Populate EL3 state so that ERET jumps to the correct entry */
2079 state = get_el3state_ctx(ctx);
2080 return read_ctx_reg(state, CTX_SCR_EL3);
2081 }
2082
2083 /*******************************************************************************
2084 * This function is used to program the context that's used for exception
2085 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
2086 * the required security state
2087 ******************************************************************************/
cm_set_next_eret_context(uint32_t security_state)2088 void cm_set_next_eret_context(uint32_t security_state)
2089 {
2090 cpu_context_t *ctx;
2091
2092 ctx = cm_get_context(security_state);
2093 assert(ctx != NULL);
2094
2095 cm_set_next_context(ctx);
2096 }
2097