refactor(st): change suffix for SYSCFG functions

This patch replaces the suffix "stm32mp1_" in the SYSCFG drivers
with "stm32mp_". By using a common suffix for function names, we can
avoid issues or

refactor(st): change suffix for SYSCFG functions

This patch replaces the suffix "stm32mp1_" in the SYSCFG drivers
with "stm32mp_". By using a common suffix for function names, we can
avoid issues or platform compilation flags when a driver
needs to access SYSCFG across different platforms.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I24407852c085abd843ef4cdef235c022a5e57a85

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feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any us

feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any users of those features in lower ELs will not trigger a trap into
BL31.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a

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feat(cpufeat): upgrade PMU to v8 (FEATURE_DETECTION)

The ARMv8 ARM J.a describes the ID_AA64DFR0_EL1.PMUver field as allowing
a maximum version number of 8 now. The added features extend the Common

feat(cpufeat): upgrade PMU to v8 (FEATURE_DETECTION)

The ARMv8 ARM J.a describes the ID_AA64DFR0_EL1.PMUver field as allowing
a maximum version number of 8 now. The added features extend the Common
event number space and clarify on some UNPREDICTABLE behaviour.

None of this affects TF-A or any system registers, so just increase the
maximum known version number to let the FEATURE_DETECTION test pass on
ARMv8.8 implementations.

Change-Id: Icab48630c1635bcd78a710b443f0db01b8ff7c9b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(st): change method to get GIC base addresses

GIC DT node structure depends on system architecture, notably around
"reg" property. A generic way to retrieve base address is needed. Use
fdt_n

refactor(st): change method to get GIC base addresses

GIC DT node structure depends on system architecture, notably around
"reg" property. A generic way to retrieve base address is needed. Use
fdt_node_offset_by_compatible() helper.

Change-Id: Ibb47864bd5e8a76a48b9346fdcf87d31281517ce
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "add_clk_callbacks" into integration

* changes:
feat(clk): add set_rate callback
feat(clk): add set_parent callback

Merge "fix(fpga): avoid stripping kernel trampoline" into integration

Merge changes from topic "rockchip" into integration

* changes:
fix(rockchip): add parenthesis for BITS_SHIFT macro
fix(rockchip): xlat: fix compatibility between v1 and v2

fix(gpt): fix GPT library fill_l1_tbl() function

GPT library function fill_l1_tbl() gets 'first' and
'last' parameters which are the start addresses of
the 1st and the last granules in the range to

fix(gpt): fix GPT library fill_l1_tbl() function

GPT library function fill_l1_tbl() gets 'first' and
'last' parameters which are the start addresses of
the 1st and the last granules in the range to fill
L1 GPT table. When RME_GPT_MAX_BLOCK build option
is not 0, condition for 'while' loop should be
changed from 'first < last' to 'first <= last' in
the case of 'first' = 'last' when a single granule
is passed.

Change-Id: I9b49a78b5a2f7a01f51dbce43bd3f3cfbb458fa2
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK

feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846

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fix(mbedtls): sign verification issue with invalid Key/Signature

When the verify_signature function is called with the RSASSA_PSS
signature algorithm and a somewhat well-formed public key, invalid
s

fix(mbedtls): sign verification issue with invalid Key/Signature

When the verify_signature function is called with the RSASSA_PSS
signature algorithm and a somewhat well-formed public key, invalid
signatures can be incorrectly verified due to this change [1].
This is primarily because of the introduction of the following code,
where a return check is missing before the goto:

if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
goto end2;
}

This code executes before the call to psa_verify_message. The
unconditional goto end2; branch leads to the immediate return of rc.
If the call to pk_bytes_from_subpubkey succeeds (i.e., the key is
formatted correctly), the signature is verified regardless of its
actual content.

This change [1] was included in the v2.11 release. Therefore, anyone
using this release with the PSA Crypto implementation must apply
this patch to ensure proper signature verification.

[1]: https://review.trustedfirmware.org/plugins/gitiles/TF-A/
trusted-firmware-a/+/55aed7d798f3d48d6aa08d58eb46c4cda318bcfb/drivers/
auth/mbedtls/mbedtls_psa_crypto.c#447

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Reported-by: Ryan Everett <ryan.everett@arm.com>
Change-Id: Ib484d97a04b7a82dd72592c8b5b153d577d01fc9

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fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "cont

fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "container with load addresses" than an object or executable
file, but it's still built with the linker tool.
Commit acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for
LTO") pulled in ${TF_LDFLAGS} when building this AXF file, which
includes "--gc-sections". That strips the kernel trampoline off that
file, making the board hang when the kernel is loaded at 0x80200000
(the recommended load address for "newer" kernels).

Drop the usage of TF_LDFLAGS altogether, since we need none of the
options specified there for our special linker step. Instead collect
the needed options (like -nostdlib) in a separate variable, and just
account for the slight syntax differences between GCC and clang.
"--strip-debug" turns out to be redundant, since "-s" already strips
more symbols, so remove that from the list.

Change-Id: I1349d58fa93973ba3add8cab2272259abdea84e0
Fixes: acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for LTO")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(clk): add set_rate callback

This callback will be used to set a clock's rate if the underlying clock
driver supports this option. The function's last parameter is an output
parameter, storing t

feat(clk): add set_rate callback

This callback will be used to set a clock's rate if the underlying clock
driver supports this option. The function's last parameter is an output
parameter, storing the actual frequency set by the clock driver, as it
may not precisely match the requested rate in some cases.

Change-Id: I6a399bf6f64407d5fbff36407561e4bf18104cf1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "st-fwu-common" into integration

* changes:
refactor(st): move FWU support to common code
refactor(st): move FWU functions to common code

Merge "feat(corstone1000): add multicore support for fvp" into integration

Merge "refactor(dice): save parent context handle" into integration

feat(clk): add set_parent callback

This callback will be used to set a clock's parent if the underlying
clock driver supports this option.

Change-Id: Ie8a77d17dd3cc867bd520217b481cd188317a9c9
Signe

feat(clk): add set_parent callback

This callback will be used to set a clock's parent if the underlying
clock driver supports this option.

Change-Id: Ie8a77d17dd3cc867bd520217b481cd188317a9c9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP man

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP manifest. Hence, this commit adds it in the SPMC
manifest.

Change-Id: I0f84d7b105c072dd021f0f2d215adf6bcdf5f98f
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

Merge "feat(versal-net): set lower cluster bus qos value" into integration

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the secondary cores.

Change-Id: Ie66b3dc43abadec88323999052357e2a9cdfd950
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Ya

refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5dde65e41908d706328cb8929582f827ceeff841

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refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_b

refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_boot_idx() to align with other ones. A new function
stm32_get_bkpr_fwu_info_addr() is created to get the backup register
address where to store FWU info (counter and partition index).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I64916c7992782ceeaaf990026756ca4134d93c88

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feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories i

feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.

Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge "feat(fvp): add cpu power control" into integration