1 /* 2 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <lib/mmio.h> 14 #include <lib/utils_def.h> 15 #include <platform_def.h> 16 #include <scmi.h> 17 18 #include "plat_private.h" 19 20 #define HIGH (1) 21 #define LOW (0) 22 23 struct scmi_clk { 24 unsigned long clock_id; 25 unsigned long rate; 26 const char *name; 27 bool enabled; 28 }; 29 30 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \ 31 [_scmi_id] = { \ 32 .clock_id = (_id), \ 33 .name = (_name), \ 34 .enabled = (_init_enabled), \ 35 .rate = (_rate), \ 36 } 37 38 static struct scmi_clk scmi0_clock[] = { 39 CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000), 40 CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000), 41 CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000), 42 CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000), 43 CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000), 44 CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000), 45 CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000), 46 CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000), 47 CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000), 48 CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000), 49 CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000), 50 CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000), 51 CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), 52 CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), 53 CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), 54 CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000), 55 CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000), 56 CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), 57 CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), 58 CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), 59 CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000), 60 CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000), 61 CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000), 62 CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000), 63 CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000), 64 CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000), 65 CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000), 66 CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000), 67 CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000), 68 CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000), 69 CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000), 70 CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000), 71 CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000), 72 CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000), 73 CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000), 74 CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000), 75 CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000), 76 CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000), 77 CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000), 78 CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000), 79 CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000), 80 CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000), 81 CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000), 82 CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000), 83 CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000), 84 CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000), 85 CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000), 86 CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000), 87 CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000), 88 CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000), 89 CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000), 90 CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000), 91 CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000), 92 CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000), 93 CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000), 94 CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000), 95 CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000), 96 CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000), 97 CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000), 98 CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000), 99 CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000), 100 CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000), 101 CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000), 102 CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000), 103 CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000), 104 CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000), 105 CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000), 106 CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000), 107 CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000), 108 CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000), 109 CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000), 110 CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000), 111 CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000), 112 CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000), 113 CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000), 114 CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000), 115 CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000), 116 CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000), 117 CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000), 118 CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000), 119 CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000), 120 CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000), 121 CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000), 122 CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000), 123 CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000), 124 CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000), 125 CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000), 126 CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000), 127 CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000), 128 CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000), 129 }; 130 131 /* 132 * struct scmi_reset - Data for the exposed reset controller 133 * @reset_id: Reset identifier in RCC reset driver 134 * @name: Reset string ID exposed to agent 135 */ 136 struct scmi_reset { 137 unsigned long reset_id; 138 const char *name; 139 }; 140 141 #define RESET_CELL(_scmi_id, _id, _name) \ 142 [_scmi_id] = { \ 143 .reset_id = (_id), \ 144 .name = (_name), \ 145 } 146 147 static struct scmi_reset scmi0_reset[] = { 148 RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"), 149 RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"), 150 RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"), 151 RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"), 152 RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"), 153 RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"), 154 RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"), 155 RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"), 156 RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"), 157 RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"), 158 RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"), 159 RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"), 160 RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"), 161 RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"), 162 RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"), 163 RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"), 164 RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"), 165 RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"), 166 RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"), 167 RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"), 168 RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"), 169 RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"), 170 RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"), 171 RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"), 172 RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"), 173 RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"), 174 RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"), 175 RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"), 176 RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"), 177 RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"), 178 RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"), 179 RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"), 180 RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"), 181 RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"), 182 RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"), 183 RESET_CELL(RESET_UFSPHY_0, RESET_UFSPHY_0, "ufsphy0"), 184 }; 185 186 struct scmi_resources { 187 struct scmi_clk *clock; 188 size_t clock_count; 189 struct scmi_reset *reset; 190 size_t reset_count; 191 192 }; 193 194 static const struct scmi_resources resources[] = { 195 [0] = { 196 .clock = scmi0_clock, 197 .clock_count = ARRAY_SIZE(scmi0_clock), 198 .reset = scmi0_reset, 199 .reset_count = ARRAY_SIZE(scmi0_reset), 200 }, 201 }; 202 203 static const struct scmi_resources *find_resource(unsigned int agent_id) 204 { 205 assert(agent_id < ARRAY_SIZE(resources)); 206 207 return &resources[agent_id]; 208 } 209 210 static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id) 211 { 212 const struct scmi_resources *resource = find_resource(agent_id); 213 size_t n = 0U; 214 struct scmi_clk *ret = NULL; 215 216 if (resource != NULL) { 217 for (n = 0U; n < resource->clock_count; n++) { 218 if (n == scmi_id) { 219 ret = &resource->clock[n]; 220 break; 221 } 222 } 223 } 224 225 return ret; 226 } 227 228 size_t plat_scmi_clock_count(unsigned int agent_id) 229 { 230 const struct scmi_resources *resource = find_resource(agent_id); 231 size_t ret; 232 233 if (resource == NULL) { 234 ret = 0U; 235 } else { 236 VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count); 237 238 ret = resource->clock_count; 239 } 240 return ret; 241 } 242 243 const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id) 244 { 245 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 246 const char *ret; 247 248 if (clock == NULL) { 249 ret = NULL; 250 } else { 251 VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name); 252 253 ret = clock->name; 254 } 255 return ret; 256 }; 257 258 /* Called by Linux */ 259 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 260 unsigned long *array, size_t *nb_elts, 261 uint32_t start_idx) 262 { 263 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 264 265 if (clock == NULL) { 266 return SCMI_NOT_FOUND; 267 } 268 269 if (start_idx > 0) { 270 return SCMI_OUT_OF_RANGE; 271 } 272 273 if (array == NULL) { 274 *nb_elts = 1U; 275 } else if (*nb_elts == 1U) { 276 *array = clock->rate; 277 VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n", 278 scmi_id, clock->name, *array); 279 } else { 280 return SCMI_GENERIC_ERROR; 281 } 282 283 return SCMI_SUCCESS; 284 } 285 286 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id) 287 { 288 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 289 unsigned long ret; 290 291 if ((clock == NULL)) { 292 ret = SCMI_NOT_FOUND; 293 } else { 294 VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate); 295 ret = clock->rate; 296 } 297 return ret; 298 } 299 300 int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id, 301 unsigned long rate) 302 { 303 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 304 unsigned long ret = UL(SCMI_SUCCESS); 305 306 if ((clock == NULL)) { 307 ret = SCMI_NOT_FOUND; 308 } else { 309 VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate); 310 clock->rate = rate; 311 } 312 return ret; 313 } 314 315 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 316 { 317 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 318 int32_t ret; 319 320 if ((clock == NULL)) { 321 ret = SCMI_NOT_FOUND; 322 } else { 323 VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled); 324 325 if (clock->enabled) { 326 ret = HIGH; 327 } else { 328 ret = LOW; 329 } 330 } 331 return ret; 332 } 333 334 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 335 bool enable_not_disable) 336 { 337 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 338 int32_t ret; 339 340 if (clock == NULL) { 341 ret = SCMI_NOT_FOUND; 342 } else { 343 if (enable_not_disable) { 344 if (!clock->enabled) { 345 VERBOSE("SCMI: clock: %u enable\n", scmi_id); 346 clock->enabled = true; 347 } 348 } else { 349 if (clock->enabled) { 350 VERBOSE("SCMI: clock: %u disable\n", scmi_id); 351 clock->enabled = false; 352 } 353 } 354 355 VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled); 356 357 ret = SCMI_SUCCESS; 358 } 359 360 return ret; 361 } 362 363 364 /* 365 * Platform SCMI reset domains 366 */ 367 static struct scmi_reset *find_reset(unsigned int agent_id, 368 unsigned int scmi_id) 369 { 370 const struct scmi_resources *resource = find_resource(agent_id); 371 size_t n; 372 373 if (resource != NULL) { 374 for (n = 0U; n < resource->reset_count; n++) { 375 if (n == scmi_id) { 376 return &resource->reset[n]; 377 } 378 } 379 } 380 381 return NULL; 382 } 383 384 const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id) 385 { 386 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 387 388 if (reset == NULL) { 389 return NULL; 390 } 391 392 return reset->name; 393 } 394 395 size_t plat_scmi_rstd_count(unsigned int agent_id) 396 { 397 const struct scmi_resources *resource = find_resource(agent_id); 398 399 if (resource == NULL) { 400 return 0U; 401 } 402 403 return resource->reset_count; 404 } 405 406 int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, 407 uint32_t state) 408 { 409 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 410 411 if (reset == NULL) { 412 return SCMI_NOT_FOUND; 413 } 414 415 /* Supports only reset with context loss */ 416 if (state != 0U) { 417 return SCMI_NOT_SUPPORTED; 418 } 419 420 NOTICE("SCMI reset on ID %lu/%s\n", 421 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 422 423 return SCMI_SUCCESS; 424 } 425 426 int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, 427 bool assert_not_deassert) 428 { 429 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 430 431 if (reset == NULL) { 432 return SCMI_NOT_FOUND; 433 } 434 435 if (assert_not_deassert) { 436 NOTICE("SCMI reset %lu/%s set\n", 437 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 438 439 switch (scmi_id) { 440 case RESET_UFS0_0: 441 mmio_write_32(PMXC_CRP_RST_UFS, 1); 442 break; 443 case RESET_UFSPHY_0: 444 mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 1); 445 break; 446 default: 447 break; 448 } 449 } else { 450 NOTICE("SCMI reset %lu/%s release\n", 451 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 452 453 switch (scmi_id) { 454 case RESET_UFS0_0: 455 mmio_write_32(PMXC_CRP_RST_UFS, 0); 456 break; 457 case RESET_UFSPHY_0: 458 mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 0); 459 break; 460 default: 461 break; 462 } 463 } 464 465 return SCMI_SUCCESS; 466 } 467 468 /* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */ 469 static struct scmi_msg_channel scmi_channel[] = { 470 [0] = { 471 .shm_addr = SMT_BUFFER_BASE, 472 .shm_size = SMT_BUF_SLOT_SIZE, 473 }, 474 }; 475 476 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 477 { 478 assert(agent_id < ARRAY_SIZE(scmi_channel)); 479 480 VERBOSE("%d: SCMI asking for channel\n", agent_id); 481 482 /* Just in case that code is reused */ 483 return &scmi_channel[agent_id]; 484 } 485 486 /* Base protocol implementations */ 487 const char *plat_scmi_vendor_name(void) 488 { 489 return SCMI_VENDOR; 490 } 491 492 const char *plat_scmi_sub_vendor_name(void) 493 { 494 return SCMI_PRODUCT; 495 } 496 497 /* Currently supporting Clocks and Reset Domains */ 498 static const uint8_t plat_protocol_list[] = { 499 SCMI_PROTOCOL_ID_BASE, 500 SCMI_PROTOCOL_ID_CLOCK, 501 SCMI_PROTOCOL_ID_RESET_DOMAIN, 502 /* 503 *SCMI_PROTOCOL_ID_POWER_DOMAIN, 504 *SCMI_PROTOCOL_ID_SENSOR, 505 */ 506 0U /* Null termination */ 507 }; 508 509 size_t plat_scmi_protocol_count(void) 510 { 511 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; 512 513 VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count); 514 515 return count; 516 } 517 518 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 519 { 520 return plat_protocol_list; 521 } 522 523 void init_scmi_server(void) 524 { 525 size_t i; 526 int32_t ret; 527 528 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) 529 scmi_smt_init_agent_channel(&scmi_channel[i]); 530 531 INFO("SCMI: Server initialized\n"); 532 533 if (platform_id == QEMU) { 534 /* default setting is for QEMU */ 535 } else if (platform_id == SPP) { 536 for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) { 537 538 /* Keep i2c on 100MHz to calculate rates properly */ 539 if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0) 540 continue; 541 /* 542 * SPP supports multiple versions. 543 * The cpu_clock value is set to corresponding SPP 544 * version in early platform setup, resuse the same 545 * value here. 546 */ 547 ret = plat_scmi_clock_set_rate(0, i, cpu_clock); 548 if (ret < 0) { 549 NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i); 550 } 551 } 552 } else { 553 /* Making MISRA C 2012 15.7 compliant */ 554 } 555 } 556