Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_paren

Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_parent callback
feat(nxp-clk): add clock objects for ARM PLL
feat(nxp-clk): add FXOSC clock enablement

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Merge "fix(arm): remove critical handoff code from assert" into integration

Merge "fix(arm): correct RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID" into integration

Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 cl

Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 clock and reset bindings
feat(st-reset): add system reset management

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fix(arm): correct RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID

The RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID macro does not match the definition
in RSE. A paired macro, TFM_CRYPTO_EXPORT_PUBLIC_KEY, in the RSE's
header

fix(arm): correct RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID

The RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID macro does not match the definition
in RSE. A paired macro, TFM_CRYPTO_EXPORT_PUBLIC_KEY, in the RSE's
header (located in interface/include/tfm_crypto_defs.h) is defined as
0x206. This causes the TF-A test PLATFORM_TEST=rse-rotpk to fail.

Correct the definition of RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID to make the
test pass.

Change-Id: I0bc24ed6dd23f2718e1edea5ec464545dab06983
Signed-off-by: Leo Yan <leo.yan@arm.com>

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fix(arm): remove critical handoff code from assert

Fix BL31 crashes caused by incorrect placement of firmware handoff code
within an assert. The function call has been removed from the assert to
ens

fix(arm): remove critical handoff code from assert

Fix BL31 crashes caused by incorrect placement of firmware handoff code
within an assert. The function call has been removed from the assert to
ensure it’s executed even when assertions are disabled.

Change-Id: I668f5c08af33327e8ff0e22887c3da109bd6be31
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(tc): add stubs for soc_css_init functions" into integration

Merge "fix(tc): don't enable TZC on TC3" into integration

Merge "fix(tc): enable MTE2 unconditionally" into integration

Merge "refactor(st): change suffix for SYSCFG functions" into integration

Merge changes Ia3549453,Ib4fa63ac,I8e918589 into integration

* changes:
refactor(spmd): move plat_my_core_pos calls
refactor(spmd): call cm_get_context once
refactor(spmd): remove spmd_get_con

Merge changes Ia3549453,Ib4fa63ac,I8e918589 into integration

* changes:
refactor(spmd): move plat_my_core_pos calls
refactor(spmd): call cm_get_context once
refactor(spmd): remove spmd_get_context_by_mpidr

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fix(stm32mp1): skip OP-TEE header check if image base is NULL

In bl2_plat_handle_post_image_load(), if the image_base of OP-TEE
header image is 0, do not call optee_header_is_valid(). This can be
th

fix(stm32mp1): skip OP-TEE header check if image base is NULL

In bl2_plat_handle_post_image_load(), if the image_base of OP-TEE
header image is 0, do not call optee_header_is_valid(). This can be
the case when OP-TEE is not present in the FIP.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic2d014e59665c9efa33bbce1bf2eb3b66cd6fb26

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Merge changes from topic "topics/ck/dependabot-alerts" into integration

* changes:
build(deps): bump certifi from 2023.7.22 to 2024.7.4
build(deps): bump idna from 3.4 to 3.7
build(deps): bump

Merge changes from topic "topics/ck/dependabot-alerts" into integration

* changes:
build(deps): bump certifi from 2023.7.22 to 2024.7.4
build(deps): bump idna from 3.4 to 3.7
build(deps): bump requests from 2.31.0 to 2.32.2
build(deps): bump jinja2 from 3.1.2 to 3.1.4
build(deps): bump urllib3 from 2.0.2 to 2.2.2
build(deps): bump pip from 23.1.2 to 23.3

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Merge "fix(intel): add in watchdog for QSPI driver" into integration

Merge "fix(qemu): remove validate_ns_entrypoint" into integration

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cac

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.

Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.

The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.

Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add support for AXP717 PMIC

On at least one new device we see an Allwinner H700 SoC paired with the
X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite
comp

feat(allwinner): h616: add support for AXP717 PMIC

On at least one new device we see an Allwinner H700 SoC paired with the
X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite
complete PMIC, with many voltage rails, battery and USB-C charging
support. It supports both RSB and I2C control options.

Add the compatible string to the list of checked devices. The AXP717
apparently does not feature a version ID register, but we read 0xff from
that address 0x3, so use this as an indication of its presence, since
this value differs from what we read from the other PMICs.
The register offset and bit position for the power off functionality is
again different, but easy to put into our switch/case.

Setting up regulators in TF-A is now somewhat obsolete, since U-Boot
does a much better job in this now, and can figure out which regulators
are actually needed. So we don't add the regulator setup code, and just
use the PMIC for the power-off functionality.

Change-Id: Ie6b4c91517014adcc79d9a3459c75545fa3a63e6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add support for AXP313 PMIC

Many newer boards with the H616 and its sibling H618 are now paired
with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few
voltage

feat(allwinner): h616: add support for AXP313 PMIC

Many newer boards with the H616 and its sibling H618 are now paired
with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few
voltage rails and no extra functionality except the power key support.
In contrast to the AXP305 it can only be controlled via I2C.

Add a check to look for the AXP313 compatible string in the devicetree,
and set the PMIC type and I2C address accordingly, if one is found.
With only very few voltage rails available, all of them are mostly in
use and are thus enabled at reset already, so we can skip the regulator
setup entirely.

Change-Id: I01962854109e43793b4f56553c1ca9e1f752e30d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's ea

feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's easier to program and also used by Linux. The AXP313a
PMIC however supports only I2C, so we need to support both buses, and
need to decide which to use at runtime.

Prepare the PMIC code to add (back) I2C support. We initially used I2C
on the H6/AXP805 combination, but replaced that later with RSB. So this
patch is bringing some of that older code back.

The decision whether to use I2C or RSB is made by the devicetree, since
on some boards even RSB capable PMICs are controlled via I2C, since they
share the bus with only I2C capable devices, for instance RTCs.

At the moment this will still use RSB to drive the AXP305, but the
(dynamic) I2C code will be used shortly to support the AXP313.

This increases the code size by one 4K page, but with 80K out of the
reserved 256K we are still very far away from our limit.

Change-Id: I65c1e7df93dbd2dcd171b3fc486533a2948cc75b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A

refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A64 with the AXP803, or the H6 with the AXP805. This allowed us to
include the respective PMIC support code into each build target at build
time.

Similarly on H616 devices we initially saw only the AXP305, but for a
while now the simpler (and cheaper) AXP313a is a popular companion to
the H616 on many new boards. On at least one new device the AXP717 is
used as well.
With some rudimentary AXP version check in place we at least detected
the case of an unsupported SoC, but threw an error message, and lost
support for powering off the device.

Refactor the existing PMIC code to be able to support more than one
PMIC model, detected at runtime. For this we use a variable for the RSB
runtime address instead of hardcoding the address used on the AXP305,
and read the hardware bus address from the devicetree.
Also we look up the used PMIC in the devicetree, and set the PMIC model
accordingly. To be on the safe side, we also confirm the real PMIC used
by checking its version register and comparing that with the expected
value. Finally the register offset and value to power off the PMIC is
moved direclty into the platform code, as those values differ between
the different PMICs.

This is just refactoring and better error report, we still only support
the AXP305 on RSB at the moment.

Change-Id: I00b26ce4d30bb570ee1cd4979d0cdc9d6c020729
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(mt8192): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas

feat(mt8192): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=132

Change-Id: I7d9444d5339f71e6bfdd9999a217e0c177e8199f
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>

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feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas

feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=149

Change-Id: I7b104c8ea8ee7f13d829a79f0a310d93ea466215
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>

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refactor(spmd): move plat_my_core_pos calls

By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even

refactor(spmd): move plat_my_core_pos calls

By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even if the result is not consumed when not
printed.
plat_my_core_pos is used to retrieve the core id for the currently
running core, but effectively call sites are only consuming it for
verbosity purposes. Move plat_my_core_pos calls into the print functions
that require it.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia3549453b5e4de7c575a8887a4d19e318658d03e

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refactor(spmd): call cm_get_context once

As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple i

refactor(spmd): call cm_get_context once

As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple individual non-inlined calls to
this same function. Store the result of cm_get_context into a local
variable and use it in the macro such that this function is only called
once.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4fa63aced2f07c67c057f54fef3780c85e91df7

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refactor(spmd): remove spmd_get_context_by_mpidr

spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including ac

refactor(spmd): remove spmd_get_context_by_mpidr

spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including access to power controller (taking/releasing a bakery lock).
Remove dependency from this function, and use plat_my_core_pos instead.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8e91858922e339de51056dba8803db74c8fd7420

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