feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent cl

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.

Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was report

fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.

Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "build: properly namespace `toolchain.mk` variables" into integration

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(tlc): add command gen-header

Introduce the gen-header command to the tool, enabling developers to
create language bindings. Currently, it supports generating C headers
from a transfer list.

Ch

feat(tlc): add command gen-header

Introduce the gen-header command to the tool, enabling developers to
create language bindings. Currently, it supports generating C headers
from a transfer list.

Change-Id: Ibec75639c38577802d5abe55c7bc718740aad2b8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(tlc): add support for tox

Add tox to automate testing across multiple environments, ensuring code
robustness and compatibility with different Python versions. This helps
ensure consistency in t

feat(tlc): add support for tox

Add tox to automate testing across multiple environments, ensuring code
robustness and compatibility with different Python versions. This helps
ensure consistency in test environments so both development and CI
systems run tests uniformly, and simplifies the execution of tasks like
linting and other commands with a single command.

Change-Id: I522adb486e89abecb9a130941ce4cef31332193a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(tlc): fix static check errors and code style

Change-Id: I8cbe5ee940d409ed3f81f792c2ade0b93287ae62
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge "refactor(mbedtls): use PSA API for auth_decrypt" into integration

Merge "fix(drtm): do cache maintenance before launching DLME" into integration

fix(drtm): do cache maintenance before launching DLME

According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance.

fix(drtm): do cache maintenance before launching DLME

According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance. However, to comply with the PSCI specification, we
decided to disable it before launching the DLME.

Also, ensure that full DLME region is invalidated.

Change-Id: Idf619afb7e4a34ebe213bd3b559105ade993f3ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(mbedtls): use PSA API for auth_decrypt

This new version uses the multipart PSA AEAD API;
the authentication tag is verified via
a call to psa_aead_verify.

Change-Id: If4b7e6258223ae6fead17

refactor(mbedtls): use PSA API for auth_decrypt

This new version uses the multipart PSA AEAD API;
the authentication tag is verified via
a call to psa_aead_verify.

Change-Id: If4b7e6258223ae6fead1794d3e8d0004f0f387b3
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS

MbedTLS 3.6.1 fixed the issue which previously
produced this warning, so this hack is no longer
necessary.

Change-Id: I934adefbf2fed16e16b9d98bc8

refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS

MbedTLS 3.6.1 fixed the issue which previously
produced this warning, so this hack is no longer
necessary.

Change-Id: I934adefbf2fed16e16b9d98bc8674125b70b08fc
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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docs(prerequisites): update MbedTLS version to 3.6.1

This new update to the LTS branch of MbedTLS provides minor
enhancements and bug fixes; including some security
fixes, and a fix to a compilation

docs(prerequisites): update MbedTLS version to 3.6.1

This new update to the LTS branch of MbedTLS provides minor
enhancements and bug fixes; including some security
fixes, and a fix to a compilation warning which
previously affected TF-A.
Full patch notes to this MbedTLS update can be found at
https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.1.

Change-Id: I1a68dfcb52a8361c1689cb6ef12d265a6462fda3
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "docs: fix ff-a manifest binding document" into integration

docs: fix ff-a manifest binding document

The support for runtime-model has never been implemented by any SPMC.
Hence, remove the corresponding field from binding document.

Also, fix the incorrect d

docs: fix ff-a manifest binding document

The support for runtime-model has never been implemented by any SPMC.
Hence, remove the corresponding field from binding document.

Also, fix the incorrect description of the `managed-exit-virq` property.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I0a5ef3f08202a8c76edd9a6e1ac680ac3a38ca60

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fix(rpi3): manually populate CNTFRQ reg

The rpi3 does not initialize the generic timer in BL1, which is now
required to use the delay timer in the dTPM driver. This change sets the
counter frequency

fix(rpi3): manually populate CNTFRQ reg

The rpi3 does not initialize the generic timer in BL1, which is now
required to use the delay timer in the dTPM driver. This change sets the
counter frequency register (CNTFRQ) with the rpi3's system counter
frequency value, as a prerequisite for timer initialization, and then
initializes the generic timer all during BL1 setup.

Change-Id: I4e2475b63ce4a97653202f94f506b5d3edc4c1a7
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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docs: update TF-A Nov'24 release dates

Planning TF-A v2.12 release in Nov'24.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0fa6885cc67e13560a79f8144bc23df6172a05c0

feat(rk3588): enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab5

feat(rk3588): enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d

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Merge "fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source" into integration

Merge "chore(gpt): fix typo in comment" into integration

fix(allwinner): enable dtb modifications for CPU idle states to the rich OS

Commit e2b18771fc2a0528dda18dbdaac08dd8530df25a ("feat(allwinner):
provide CPU idle states to the rich OS") added function

fix(allwinner): enable dtb modifications for CPU idle states to the rich OS

Commit e2b18771fc2a0528dda18dbdaac08dd8530df25a ("feat(allwinner):
provide CPU idle states to the rich OS") added functionality to amend
dtb, when SCPI as the PSCI backend is available. But this
functionality is disabled by default even for platforms, that support
it, like A64. As a result rich OS don't get information about
available CPU idle states.

Due to size constraints of A64 platform DEBUG=1 can be built with
dtb amend functionality only with LTO enabled. So ENABLE_LTO is
enabled by default for this platform.

```
aarch64-linux-gnu-ld.bfd: address 0x500dd of build/sun50i_a64/debug/bl31/bl31.elf section `.data' is not within region `RAM'
aarch64-linux-gnu-ld.bfd: BL31 image has exceeded its limit.
aarch64-linux-gnu-ld.bfd: region `RAM' overflowed by 224 bytes
```

To build with ENABLE_LTO=0 and DEBUG=1 it's required SUNXI_AMEND_DTB=0
to explicitly disable dtb amend functionality.

sun50i_r329 SUNXI_AMEND_DTB=1 DEBUG=1 build fails with 'region `RAM'
overflowed by 120 bytes'. To avoid unnecessary RAM consumption on
other resource-constraints platforms (like sun50i_r329)
SUNXI_AMEND_DTB is enabled only on sun50i_a64. Otherwise
On other platforms sunxi_idle_states are empty.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: I81fcf31b5bd2bd02a9f3361a6a519632f087445d

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feat(build): add ability to define platform specific defaults

In some cases it maybe needed to override some default settings on a
particular platform. For example, enable ENABLE_LTO on a size
const

feat(build): add ability to define platform specific defaults

In some cases it maybe needed to override some default settings on a
particular platform. For example, enable ENABLE_LTO on a size
constrained platform.

Change-Id: I556d26f6b81c0f3ceb40b7196180995dde22afd0
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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chore(gpt): fix typo in comment

Fix a confusing typo in comment docstring.

Change-Id: I9424454b9fa140bf6a482dea7f8cba24806068b6
Signed-off-by: Moritz Fischer <moritzf@google.com>

Merge "fix(xilinx): warn if reserved memory pre-exists in DT" into integration