feat(versal): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and

feat(versal): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.

Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.

The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios.

Change-Id: I7b71fb4a8cd36e8e91c98ebee09904ba47222e33
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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refactor(xilinx): register runtime console directly

Initialize runtime console early instead of deferred init.

Change-Id: Iae2f69ba4da27b62b69d640e3ccdc1303f549617
Signed-off-by: Michal Simek <mich

refactor(xilinx): register runtime console directly

Initialize runtime console early instead of deferred init.

Change-Id: Iae2f69ba4da27b62b69d640e3ccdc1303f549617
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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refactor(xilinx): console registration through console holder structure

Refactored register_console using console holder structure as
input. Structure holds console scope and console type as additio

refactor(xilinx): console registration through console holder structure

Refactored register_console using console holder structure as
input. Structure holds console scope and console type as additional
members. These modifications enhance code readability and
maintainability, contributing to a clearer and more sustainable
codebase for future development.

Change-Id: I7fcc1accfdecdacc205d427a80031536c456638e
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(zynqmp): add DTB console to platform.mk

In the platform.mk file, new console types named dtb are to be created
a macro, ZYNQMP_CONSOLE_ID_dtb, will be introduced to check DT console.
Users will

feat(zynqmp): add DTB console to platform.mk

In the platform.mk file, new console types named dtb are to be created
a macro, ZYNQMP_CONSOLE_ID_dtb, will be introduced to check DT console.
Users will have the option to select ZYNQMP_CONSOLE to dtb, which will
run from the DDR address. The address XILINX_OF_BOARD_DTB_ADDR needs
to be provided. This configuration will register the DT console in TF-A.
Flags for the ZynqMP platform and other AMD-Xilinx platforms will be
updated to utilize common code.

Change-Id: If74da4a80196575335c9d5562e6d8cd12d99561c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(zynqmp): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and

feat(zynqmp): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.

Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.

The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios.

Change-Id: I32913dede3d87109e54d179e7d99f45c33b9097b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(xilinx): dcc to support runtime console scope

DCC driver to support boot and runtime console scope
switch for dedicated boot and runtime consoles.

Change-Id: I7769dc44860a5fda99ca42ce17a3a60092

fix(xilinx): dcc to support runtime console scope

DCC driver to support boot and runtime console scope
switch for dedicated boot and runtime consoles.

Change-Id: I7769dc44860a5fda99ca42ce17a3a6009288d7e7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the

feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switchin

feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GIC

fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GICR_WAKER.ProcessorSleep bit is set. There is an "assert" in the
GIC setup function to check this.
However when using RESET_TO_BL31, there might be prior firmware running,
and it might have used the GIC already. This is for instance the case on
the Allwinner A523 SoC, where the BootROM initialises the GIC to use it
when handling the built-in USB debug protocol.

Drop the assert, which is not the right thing to do here anyway: it's
not checking an internal state. Instead return early when the
redistributor is already marked as active.
Also keep waiting if ChildrenAsleep is unexpectedly set, but warn about
this.

This fixes booting TF-A on an Allwinner A523 SoC when using the USB
debug mode.

Change-Id: I5be9e1b0489d33b8371fff484e526483d5f3d937
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(s32g274a): add ncore support" into integration

Merge "docs: deprecate Arm TC2 FVP platform" into integration

fix(versal2): correct the UFS clock rates

Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock

fix(versal2): correct the UFS clock rates

Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock rate for these two clocks.
- cpu_clock rate (908KHz) is not valid clock for UFS, hence skip setting
up UFS clocks to cpu_clock for SPP platform.

Change-Id: I31863619ca1bd527df283d1636493dd8fce18809
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U

feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U-Boot).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic79429c3bd4516c339f91a10e0b3f2828bf6c392

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feat(tc): move flash device to own node

Move the flash address to its own devicetree node in
tc_spmc_manifest.dtsi. This patch also changes the device-type to
ns-device-memory which is the correct t

feat(tc): move flash device to own node

Move the flash address to its own devicetree node in
tc_spmc_manifest.dtsi. This patch also changes the device-type to
ns-device-memory which is the correct type for a flash device.

Change-Id: I19503ac35c433661faaaa01c0b83a16540d73810
Co-developed-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge "fix(st-ddr): fix coverity issue in ddrphyinit" into integration

fix(st-ddr): fix coverity issue in ddrphyinit

Address issue CID 445362 and CID 445361 found during coverity scan.

Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <ma

fix(st-ddr): fix coverity issue in ddrphyinit

Address issue CID 445362 and CID 445361 found during coverity scan.

Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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docs(maintainers): update qti maintainer

Add Saurabh Gorecha in qti maintainer

Change-Id: I24c8453288444ec9f60dca7c4019fd1635090b33
Signed-off-by: Bharath N <quic_bharn@quicinc.com>

feat(stm32mp2-fdts): update STM32MP257F-EV1 DT

Add include for DDR configuration, and reference to OTP storing the
board ID.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf

feat(stm32mp2-fdts): update STM32MP257F-EV1 DT

Add include for DDR configuration, and reference to OTP storing the
board ID.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf1dac77b91b2c148ec4dc1fb7b76631

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feat(fdts): add DDR4 files for STM32MP2

These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.ga

feat(fdts): add DDR4 files for STM32MP2

These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iec73f9c5028f897624125082bdb591274aad3afc

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feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node

Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed prop

feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node

Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed properties.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ie63f48dcacefe590c68cf6ec694d9e82349cece8

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feat(stm32mp25-fdts): add DDR power supplies

Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.

Signed-off-by: Patrick Delaunay <patrick.delaunay@

feat(stm32mp25-fdts): add DDR power supplies

Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I951da75a554bc4fbfbc69ea9cd1171d99ed7ce46

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feat(stm32mp2-fdts): add memory node

Add ddr node in stm32mp251.dtsi file, which gives addresses to DDR PHY
and DDR controller.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I719bfd1

feat(stm32mp2-fdts): add memory node

Add ddr node in stm32mp251.dtsi file, which gives addresses to DDR PHY
and DDR controller.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I719bfd1640a8217ff79e79b5b53845b75421d298

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feat(stm32mp2): enable DDR driver

Call stm32mp2_ddr_probe() function in platform setup.
Move DDR systematic test file in common.mk.

Change-Id: I982abd33635a3222a52c967eac64676bc26b0d6b
Signed-off-b

feat(stm32mp2): enable DDR driver

Call stm32mp2_ddr_probe() function in platform setup.
Move DDR systematic test file in common.mk.

Change-Id: I982abd33635a3222a52c967eac64676bc26b0d6b
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(imx8m): ensure domain permissions for the console

The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with
enum type") also hardcodes the domain permissions configuration for the
UA

fix(imx8m): ensure domain permissions for the console

The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with
enum type") also hardcodes the domain permissions configuration for the
UARTs, causing a regression for any board using a boot console different
from UART2. Indeed, previously, the RDC_PDAP_UARTn registers were set to
the reset value (0xff), meaning all domains were enabled for read and
write access.

This patch fixes this regression by ensuring that the console always has
read/write access enabled for domain 0.

Tested on a i.MX8MN BSH SMM S2 PRO board.

Fixes: d76f012ea8fc0 ("refactor(imx8m): replace magic number with enum type")
Change-Id: I2670bf485372f32ef45cebb72a7694a9a800f417
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

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refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

Change-Id: Ie6a4555a659e9f722a8d819958ad9a2dee7c3aa0
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

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