feat(lfa): allow LFA_PRIME from one CPU at a time

LFA_PRIME is a single-threaded operation that is not pinned
to a specific CPU. The implementation must support calls being
issued from different CPU

feat(lfa): allow LFA_PRIME from one CPU at a time

LFA_PRIME is a single-threaded operation that is not pinned
to a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime
the same component. However, those calls must not happen
concurrently.

This patch introduces a spinlock across the LFA_PRIME call to
support this requirement. In case of concurrent calls, the
LFA_BUSY error code is returned to the caller.

Change-Id: I0574a155ea66b527e26b0dd73272a103e4f936b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): w

Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): workaround for Cortex-A715 erratum 2409570

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Merge "fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2" into integration

fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boya

fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan

fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tspd): don't forward declare tsp_vectors_t

Everyone who needs it can (and does) include tsp.h which has the whole
definition.

Building with clang throws up errors otherwise.

Change-Id: Ibb05dd

fix(tspd): don't forward declare tsp_vectors_t

Everyone who needs it can (and does) include tsp.h which has the whole
definition.

Building with clang throws up errors otherwise.

Change-Id: Ibb05dd47fdc135f3110ea4c4744f675ce7e81184
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): drop feature_panic() as unused

We've grown out of it and it's sitting unused. The compiler emits a
warning for the dead code and the build fails.

Change-Id: Icec70861936b7101e8aca0b67

fix(cpufeat): drop feature_panic() as unused

We've grown out of it and it's sitting unused. The compiler emits a
warning for the dead code and the build fails.

Change-Id: Icec70861936b7101e8aca0b67c71a2c81dd9c59c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "build(dev-deps): bump pyright" into integration

Merge changes from topic "st-usb-coverity" into integration

* changes:
fix(st-usb): init endpoint with fixed value if only one is used
fix(st-usb): correct phy_epnum type for error trace
fix(s

Merge changes from topic "st-usb-coverity" into integration

* changes:
fix(st-usb): init endpoint with fixed value if only one is used
fix(st-usb): correct phy_epnum type for error trace
fix(st-usb): stub dead code

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build(dev-deps): bump pyright

Bumps the dev-deps group with 1 update in the /tools/memory directory: [pyright](https://github.com/RobertCraigie/pyright-python).


Updates `pyright` from 1.1.406 to 1

build(dev-deps): bump pyright

Bumps the dev-deps group with 1 update in the /tools/memory directory: [pyright](https://github.com/RobertCraigie/pyright-python).


Updates `pyright` from 1.1.406 to 1.1.407
- [Release notes](https://github.com/RobertCraigie/pyright-python/releases)
- [Commits](https://github.com/RobertCraigie/pyright-python/compare/v1.1.406...v1.1.407)

--
updated-dependencies:
- dependency-name: pyright
dependency-version: 1.1.407
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
...

Change-Id: I85f9e800788ddeafef4194b6a40785a81cebe0a8
Signed-off-by: dependabot[bot] <support@github.com>

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feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_entries and create
`plat_fiptool.mk` in order to enable the integration
of the DDR FW binary into the FIP image using
`fiptool` command.

Change-Id: I10c000025378206411ab70dbc5b2e745ffb01e5d
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(fiptool): skip Layerscape makefile for S32 build

Skip Layerscape makefile for S32CC platform.
This change ensures the `fiptool` Makefile
recognizes and process the S32-specific Makefile
correctl

fix(fiptool): skip Layerscape makefile for S32 build

Skip Layerscape makefile for S32CC platform.
This change ensures the `fiptool` Makefile
recognizes and process the S32-specific Makefile
correctly, instead of the default Layerscape one.

Change-Id: I09b54a676d8db035c41ad77325b5b0e4b230e1ac
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation

fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Iad149a2c02a804b3f4f0f2f5b89e866675cb4093
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected t

fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected to have a significant performance
impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Idcd2a07d269d55534dc5faa59c454d37426f2cfa
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a sign

fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a significant performance impact for
software that relies heavily on using store-release instructions.

This workaround only applies to r1p0, r0p0 has a different
workaround but is not used in production hardware so has not been
implemented.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Id9429831525b842779d7b7e60f103c93be4acd67
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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Merge "feat(mt8196): enable MTE2" into integration

Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols un

Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols until all are resolved
fix(build): add include directory dependencies

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feat(mt8196): enable MTE2

Enable the Memory Tagging Extension (MTE) feature for the MediaTek
mt8196 platform by setting ENABLE_FEAT_MTE2 to 1 in the platform
configuration. This enables MTE support

feat(mt8196): enable MTE2

Enable the Memory Tagging Extension (MTE) feature for the MediaTek
mt8196 platform by setting ENABLE_FEAT_MTE2 to 1 in the platform
configuration. This enables MTE support at EL1 and EL2.

Change-Id: Iafe4e89ad33d0834ea630009620a605ac36e0be3
Signed-off-by: Yidi Lin <yidilin@google.com>

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Merge "fix(morello): fix the incorrect order of gpu interrupts in dt" into integration

fix(morello): fix the incorrect order of gpu interrupts in dt

Declare the GPU DT interrupts in the same order as defined
in the DT schema for arm,mali-bifrost.

Signed-off-by: Chandni Cherukuri <cha

fix(morello): fix the incorrect order of gpu interrupts in dt

Declare the GPU DT interrupts in the same order as defined
in the DT schema for arm,mali-bifrost.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: If3e72d33dcba4143900a5032688cf9340c717259

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Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to

Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to v1.7.2

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Merge "fix(rcar4): assure SCIF and HSCIF clock are always enabled" into integration

Merge "fix(cpufeat): use of additional breakpoints" into integration