fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT

Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binari

fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT

Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binaries and FIP in a single command. Else, as TOOL_ADD_IMG evaluate
the existence of the file before building it, we have a build error.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I72d2f70733c49792d0321ad07f5a3bbd283a36d4

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fix(stm32mp2): enable timer earlier in BL31

The timer is required when setting console. In BL2 the timer init is
done in clock driver init. This is not the case in BL31. So initialize
the generic_de

fix(stm32mp2): enable timer earlier in BL31

The timer is required when setting console. In BL2 the timer init is
done in clock driver init. This is not the case in BL31. So initialize
the generic_delay_timer_init() just after stm32mp2_clk_init() call.
This is required after the recent changes in timer framework [1].

[1]: a6485b2b3b refactor(delay-timer): add timer callback functions

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e84a45fc526ed132e97b238596aa69ddfc2b058

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docs(juno): update Juno tested SCP version to 2.15

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I29452d0abadf9b5980ca9680ca2c78080c4c33a0

Merge "fix(build): ensure `$(ROT_KEY)` depends on correct directory rules" into integration

fix(build): ensure `$(ROT_KEY)` depends on correct directory rules

In order for directories to be automatically created when used as a
dependency, they must end with a forward slash (`/`). This is b

fix(build): ensure `$(ROT_KEY)` depends on correct directory rules

In order for directories to be automatically created when used as a
dependency, they must end with a forward slash (`/`). This is because we
have a pattern rule (`%/`) to create a directory anywhere where a
directory is required as a direct dependency.

Change-Id: Ib632d59da0745f6cadb0a839a62360aeca25c178
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(tc): fix the MHUv3 interrupt name in DT

Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.

Signed-off-by: Leo Yan <leo.yan@arm.c

fix(tc): fix the MHUv3 interrupt name in DT

Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I8d2da2dd0e9dac2bed3963efc695a277bb5e14bd

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fix(imx8m): fix imx8mq build break

Fix the build break for i.MX8MQ to make it boot
with basic function enabled.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2ff7976e3fb7960d6876d26fe0b4a

fix(imx8m): fix imx8mq build break

Fix the build break for i.MX8MQ to make it boot
with basic function enabled.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2ff7976e3fb7960d6876d26fe0b4a78e51219ae2

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fix(imx8mq): fix imx8mq build break due to hab

Add the HAB secure boot support for the i.MX8MQ to
fix the build break.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I806de2dc42806e008355cc

fix(imx8mq): fix imx8mq build break due to hab

Add the HAB secure boot support for the i.MX8MQ to
fix the build break.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I806de2dc42806e008355cc185065e774570362f0

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fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fi

fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fits due to its size, and where it makes use of
non-volatile PMIC registers to alternate between loading and
starting A or B copy of the BL2. The PMIC registers are used
because CPU registers are lost across reset.

In case the B copy is loaded, it is loaded from 8 MiB offset
from start of HF. In case the B copy fails to boot, a simple
reset of the system will switch back to booting previously
known working A copy and allow recovery.

The A/B loader sets MFIS bit MFISBTSTSR_BOOT_PARTITION to
pass the information which A/B copy is currently booting on
to TFA, which then loads the follow up components from 0 MiB
or 8 MiB offset, depending on whether the A or B copy is being
booted.

The MFISBTSTSR_BOOT_PARTITION interferes with regular A/B
switching during boot from eMMC as the boot media, where
the BootROM also sets MFISBTSTSR_BOOT_PARTITION bit in case
the system boots from SECOND eMMC HW BOOT partition.

Since the A/B loader is meant as a development and CI tool,
isolate the A/B loader use to RPC HF only and furthermore
isolate it behind new RCAR_RPC_HYPERFLASH_ABLOADER option
which is disabled by default.

[1] https://github.com/marex/abloader

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04ecd50fa1405b78e1ba3949d54029034d4f22d8

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fix(rcar-layout): fix tool build

Since 2f1c5e7eb177 ("build: use GCC to link by default") the
code does not even compile with GCC14 on debian/unstable with
the following error:

/usr/lib/gcc-cross/a

fix(rcar-layout): fix tool build

Since 2f1c5e7eb177 ("build: use GCC to link by default") the
code does not even compile with GCC14 on debian/unstable with
the following error:

/usr/lib/gcc-cross/aarch64-linux-gnu/14/../../../../aarch64-linux-gnu/bin/ld: bootparam_sa0.elf: error: PHDR segment not covered by LOAD segment
/usr/lib/gcc-cross/aarch64-linux-gnu/14/../../../../aarch64-linux-gnu/bin/ld: cert_header_sa6.elf: error: PHDR segment not covered by LOAD segment

Fix the tools build.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I830b53e23f25c62da3583c1c3e02e0607a237d15

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Merge "fix(mbedtls): fix error return code for calc_hash" into integration

Merge "feat(cm): test integrity of el1_ctx registers" into integration

fix(intel): add FPGA isolation trigger when reconfiguration

This change is to add in new Mailbox CMD to SDM for MPFE isolation.

Change-Id: I52c84dc227e1c8edbded63c699ded63e431d9af2
Signed-off-by: S

fix(intel): add FPGA isolation trigger when reconfiguration

This change is to add in new Mailbox CMD to SDM for MPFE isolation.

Change-Id: I52c84dc227e1c8edbded63c699ded63e431d9af2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-of

fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(mbedtls): fix error return code for calc_hash

Make this function return values from crypto_ret_value.
The previous method of returning the mbedtls error code
on failure meant that the authentica

fix(mbedtls): fix error return code for calc_hash

Make this function return values from crypto_ret_value.
The previous method of returning the mbedtls error code
on failure meant that the authentication module couldn't
correctly parse failures from this function.

Change-Id: I9fe6eba1fc79e8f81004f8cd202781aea907e963
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(build): correct feature assignment for ARM v8.8 compliance" into integration

Merge "fix(arm): load dt before updating entry point" into integration

Merge changes If56ed0ab,I632236a1 into integration

* changes:
perf(build): don't check the compiler's flags for every target
perf(build): be clever about uppercasing

perf(build): don't check the compiler's flags for every target

The TF_FLAGS variable must be recursively expanded as the rules that use
it are defined before it has been fully defined. That has the

perf(build): don't check the compiler's flags for every target

The TF_FLAGS variable must be recursively expanded as the rules that use
it are defined before it has been fully defined. That has the
unfortunate side effect of spawning a subshell that calls the compiler
for every file that is being built, thrashing multicore build times.

We don't cater to the possibility of the toolchain changing mid build so
precomputing this value would be more sensible. Doing a clean build on
an Intel dual socket Xeon Gold 5218 (i.e. 64 threads) workstation used
to take about 9 seconds. After this patch it takes about 1.5. Single
core performance went from ~45 seconds to about 25.

Change-Id: If56ed0ab3cc42bc482d9dd05a41ffbff4dd7f147
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(build): be clever about uppercasing

Most of the macros in build_macros.mk get lazily evaluated. That's
mostly fine, except for the fact that the `uppercase` macro needs to
spawn a subshell to g

perf(build): be clever about uppercasing

Most of the macros in build_macros.mk get lazily evaluated. That's
mostly fine, except for the fact that the `uppercase` macro needs to
spawn a subshell to get its output. And the target for every file
requires calling `uppercase` many, MANY, times, thrashing performance on
even the most trivial of make commands.

We can be a little clever and only call `uppercase` a handful of times
and then pass around the already uppercased strings.

The same is true about the verbosity augmentation variables. Simply
changing them to simply expanded variables allows for them to be
pre-processed and then used over and over again.

`make realclean` is a pretty good benchmark for this as it doesn't do
much else but must process all the rules, like every other make command.
On a clean checkout of TF-A on an Intel Xeon Gold 5218 (i.e. slow
single-core) workstation, that command used to take about 7 seconds.
With this patch it takes about 0.5.

Change-Id: I632236a12a40f169e834974ecbc73ff80aac3462
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cm): test integrity of el1_ctx registers

* This patch adds support to tsp (BL32) Image, to exercise
EL1_context registers at S-EL1.

* Adds a SMC function ID "MODIFY_EL1_CTX" to handle EL1_CT

feat(cm): test integrity of el1_ctx registers

* This patch adds support to tsp (BL32) Image, to exercise
EL1_context registers at S-EL1.

* Adds a SMC function ID "MODIFY_EL1_CTX" to handle EL1_CTX
registers at S-EL1 and overwrite them.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Id4f2b3b748f7bc9e6c9d72a2f03d50aefbfb61cb

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fix(build): correct feature assignment for ARM v8.8 compliance

Correct feature list assignment to apply ARM v8.7 features
to `armv8-8-a-feats` instead of `armv8-7-a-feats` for ARM v8.8
compliance.
T

fix(build): correct feature assignment for ARM v8.8 compliance

Correct feature list assignment to apply ARM v8.7 features
to `armv8-8-a-feats` instead of `armv8-7-a-feats` for ARM v8.8
compliance.
This was highlighted during the build of TC4 with ARM_ARCH_MAJOR=8
and ARM_ARCH_MINOR=8.

Change-Id: I6c48a3ffa2f1e18d5e4a6484a823c9112dddd751
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "build(bl31): support separated memory for RW DATA" into integration

Merge "feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA" into integration

Merge "fix(psa): fix P-384 PSA key signature verification" into integration