feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off

feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-of

feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id:

feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.

feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(cm): change back owning security state when a feature is disabled" into integration

perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inli

perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.

Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(psci): move timestamp collection to psci_pwrdown_cpu

psci_pwrdown_cpu has two callers, both of which save timestamps meant to
measure how much time the cache maintenance operations take. Mo

refactor(psci): move timestamp collection to psci_pwrdown_cpu

psci_pwrdown_cpu has two callers, both of which save timestamps meant to
measure how much time the cache maintenance operations take. Move the
timestamp collection inside to save on a bit of code duplication.

Change-Id: Ia2e7168faf7773d99b696cbdb6c98db7b58e31cf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(psci): factor common code out of the standby finisher

psci_suspend_to_standby_finisher and psci_cpu_suspend_finish do mostly
the same stuff, besides the system management associated with th

refactor(psci): factor common code out of the standby finisher

psci_suspend_to_standby_finisher and psci_cpu_suspend_finish do mostly
the same stuff, besides the system management associated with their
respective wakeup paths. So bring the wake from standby path in line
with the wake from reset path - caller acquires locks and manages
context. This way both behave in vaguely the same way. We can also bring
their names in line so it's more apparent how they are different.

This is in preparation for cores waking from sleep, coming in another
patch. No functional change is expected.

Change-Id: I0e569d12f65d231606080faa0149d22efddc386d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state

The target_pwrlvl field in the psci cpu data struct only stores the
highest power domain that a CPU_SUSPEND call affected, and is u

refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state

The target_pwrlvl field in the psci cpu data struct only stores the
highest power domain that a CPU_SUSPEND call affected, and is used to
resume those same domains on warm reset. If the cpu is otherwise OFF
(never turned on or CPU_OFF), then this needs to be the highest power
level because we don't know the highest level that will be off.

So skip the invalidation and always keep the field to the maximum value.
During suspend the field will be lowered to the appropriate value and
then put back after wakeup.

Also, do that in the suspend to standby path as well as it will have
been written before the sleep and it might end up incorrect.

Change-Id: I614272ec387e1d83023c94700780a0f538a9a6b6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(psci): drop outdated cache maintenance comment

The comment was written when cache maintenance had to be considered when
calling this function. But that argument was dropped a while back and
thi

docs(psci): drop outdated cache maintenance comment

The comment was written when cache maintenance had to be considered when
calling this function. But that argument was dropped a while back and
this comment no longer makes any sense.

Change-Id: Ib68293f23cc3edca3010164dfe8866956b8e1a63
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cm): change back owning security state when a feature is disabled

Patch fc7dca72ba656e5f147487b20f9f0fb6eb39e116 changed the owning
security states of the TRBE and SPE buffers to NS. The thinkin

fix(cm): change back owning security state when a feature is disabled

Patch fc7dca72ba656e5f147487b20f9f0fb6eb39e116 changed the owning
security states of the TRBE and SPE buffers to NS. The thinking was that
this would assist SMCCC feature availability to more easily determine
if the feature is enabled or disabled. However, that only changed bit 0
while the SMCCC feature only looks at bit 1 so this change is redundant.

It was also meant to tighten security but that was done by
73d98e37593f4a4044dd28f52127cdc890911c0c instead.

Annoyingly, FEAT_TRBE has TRBIDR_EL1 which reports that programming is
allowed when the current security state owns the buffer even when the
MDCR_EL3 setting disallows this in practice.

So revert the functional aspect of the patch as it causes linux panics
with ERRATA_A520_2938996. Keep the defines as they are used elsewhere.

Change-Id: I39463d585df89aee44d1996137616da85d678f41
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(mediatek): add gic driver

Add GIC driver for taking interrupts to core.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: Id4d702b8579488befc1a1b6d37e66287dd534798

Merge "fix(intel): handle cold reset via physical reset switch" into integration

Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add

Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64
feat(el3-spmc): support Hob list to boot S-EL0 SP
feat(synquacer): add support Hob creation
fix(fvp): exclude extend memory map TZC regions
feat(fvp): add StandaloneMm manifest in fvp
feat(spm): use xfer list with Hob list in SPM_MM

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Merge "feat(mt8196): link prebuilt library" into integration

Merge "feat(mt8196): add Mediatek EMI stub implementation for mt8196" into integration

feat(el3_spmc): ffa error handling in direct msg

When an FFA_ERROR happens while handling a direct message
from normal world, return to normal world with
FFA_ERROR. Otherwise, the system would re-en

feat(el3_spmc): ffa error handling in direct msg

When an FFA_ERROR happens while handling a direct message
from normal world, return to normal world with
FFA_ERROR. Otherwise, the system would re-enter the secure partition
with FFA_ERROR.

Change-Id: I3d9a68a41b4815c1a8e10354cfcf68fec9f4b800
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>

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feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2

StandaloneMm which is S-EL0 partition uses
FFA_MSG_SEND_DIRECT_REQ2/RESP2 to handle multiple services.
For this, add support for FFA_MSG_SEND_DIREC

feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2

StandaloneMm which is S-EL0 partition uses
FFA_MSG_SEND_DIRECT_REQ2/RESP2 to handle multiple services.
For this, add support for FFA_MSG_SEND_DIRECT_REQ2/RESP2 in el3_spmc
restrictly up to use 8 registers.
although FF-A v1.2 defines FFA_MSG_SEND_DIRECT_REQ2/RESP2
with ability to pass/return up to 18 registers.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I8ab1c332d269d9d131330bb2debd10d75bdba1ee

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fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bit

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.

Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.

Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <g

fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(mt8196): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided by
MTKLIB_PATH. Otherwise, it will use stub implementation.

Change-Id: I218e724231c8bbc6cc851

feat(mt8196): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided by
MTKLIB_PATH. Otherwise, it will use stub implementation.

Change-Id: I218e724231c8bbc6cc851a240c6bbc4f6f49f154
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>

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feat(el3-spmc): use spmd_smc_switch_state after secure interrupt

Switch the state back to non-secure after a secure interrupt
using spmd_smc_switch_state with FFA_NORMAL_WORLD_RESUME
to reduce the n

feat(el3-spmc): use spmd_smc_switch_state after secure interrupt

Switch the state back to non-secure after a secure interrupt
using spmd_smc_switch_state with FFA_NORMAL_WORLD_RESUME
to reduce the number of control flow paths for world switches.
Fixes an issue where FP registers were not correctly restored
after secure interrupts.

Upstreamed from https://r.android.com/3345999, tested on Trusty.

Change-Id: I3ce33f7657c13b999969ebb8957d5d4b6c3aa634
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a70

refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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docs(gxl): add build instructions for booting BL31 from U-Boot SPL

Change-Id: Ided750decea924ff8d78d2d345d34bc40b05f0cb
Signed-off-by: Ferass El Hafidi <funderscore@postmarketos.org>