feat(cpus): add ENABLE_ERRATA_ALL flag

Now that all errata flags are all conveniently in a single list we can
make sweeping decisions about their values. The first use-case is to
enable all errata i

feat(cpus): add ENABLE_ERRATA_ALL flag

Now that all errata flags are all conveniently in a single list we can
make sweeping decisions about their values. The first use-case is to
enable all errata in TF-A. This is useful for CI runs where it is
impractical to list every single one. This should help with the long
standing issue of errata not being built or tested.

Also add missing CPUs with errata to `ENABLE_ERRATA_ALL` to enable all
errata builds in CI.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2b456d304d7bf3215c7c4f4fd70b56ecbcb09979

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Merge "fix(mt8196): remove CPU_IDLE_SRAM_BASE entry from plat_mmap" into integration

Merge "feat(mediatek): update mtk_sip_def.h" into integration

Merge "feat(tc): enable Arm SPE for TC4" into integration

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths

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Merge "fix(el3-runtime): for nested serrors, restore x30 to lower EL address" into integration

Merge "fix(versal2): update DDR address map" into integration

Merge "feat(versal2): update platform version to versal2" into integration

fix(psci): check if a core is the last one in a requested power level

PSCI OS initiated is usually implemented with the extended state id
format, however this does not have to be the case. When this

fix(psci): check if a core is the last one in a requested power level

PSCI OS initiated is usually implemented with the extended state id
format, however this does not have to be the case. When this is the
case, the original format will carry the requested power level in
the PowerLevel field. To validate that the requested power state is
valid we must save it so that later when we call
psci_is_last_cpu_to_idle_at_pwrlvl() it checks the right level (instead
of a default 0).

This came up when testing 01959a1656a08dacd1d036d0441165d52bf7563e for
all configurations.

Change-Id: Iaab88c1910467282ae524861446283acddd9d977
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(mt8196): remove CPU_IDLE_SRAM_BASE entry from plat_mmap

This region is defined in LPM driver. Prefer managing this region in
LPM driver and remove it from plat_mmap and platform_def.h.

Change-I

fix(mt8196): remove CPU_IDLE_SRAM_BASE entry from plat_mmap

This region is defined in LPM driver. Prefer managing this region in
LPM driver and remove it from plat_mmap and platform_def.h.

Change-Id: I57bfaad88a28d4f29e2b132ba080bc7d5b8248d8
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(mediatek): update mtk_sip_def.h

Update missing SiP SCM ID definitions. Those definitons are required
when linking to the proprietary library.

Change-Id: I6b912cee9bcceac774ff2228a1e335073a1d5e

feat(mediatek): update mtk_sip_def.h

Update missing SiP SCM ID definitions. Those definitons are required
when linking to the proprietary library.

Change-Id: I6b912cee9bcceac774ff2228a1e335073a1d5ea7
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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Merge "fix(mt8196): add whole-archive option to prebuilt library" into integration

fix: add support for 128-bit sysregs to EL3 crash handler

The following changes have been made:
* Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm
* Add registers TTBR0_EL2 and

fix: add support for 128-bit sysregs to EL3 crash handler

The following changes have been made:
* Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm
* Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output
* Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1,
VTTBR_EL2 and PAR_EL1

Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

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Merge changes I65b9e341,I7f3c42cb,I1bb1771d into integration

* changes:
feat(mt8196): add reset and poweroff function for PSCI call
feat(mt8196): refactor LPM header include paths to use lpm_v2

Merge changes I65b9e341,I7f3c42cb,I1bb1771d into integration

* changes:
feat(mt8196): add reset and poweroff function for PSCI call
feat(mt8196): refactor LPM header include paths to use lpm_v2
refactor(mediatek): update API calls to MTK GIC v3 driver

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fix(el3-runtime): for nested serrors, restore x30 to lower EL address

In FFH mode, When handling nested serrors, serror is handled once and
all subsequent serrors are considered handled.And EL3 dire

fix(el3-runtime): for nested serrors, restore x30 to lower EL address

In FFH mode, When handling nested serrors, serror is handled once and
all subsequent serrors are considered handled.And EL3 directly return
to lower EL.

While returning to lower EL, x30 is restore to CTX_SAVED_GPREG_LR
address.CTX_SAVED_GPREG_LR address belongs to EL3 address range and
this address will not be accessible in lower EL.

After return to lower EL, when lower EL access x30, segmentation fault
happens and Kernel kills application.

This patch restore x30 to lower EL address (CTX_GPREG_LR) to avoid
segmentation fault at lower EL.

Change-Id: Ie8becb206e0c0204e01d12ab63ae6e915dcf33e4
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

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Merge "docs(context-mgmt): remove redundant information" into integration

feat(mt8196): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I65b9e341b74f568f968f3c464a64ea754284cb8c
Signed-off-by: Yidi Lin <yidilin@chro

feat(mt8196): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I65b9e341b74f568f968f3c464a64ea754284cb8c
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add

Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add get_rate for partition objects
feat(nxp-clk): add get_rate for clock muxes
feat(nxp-clk): add get_rate for s32cc_pll_out_div
feat(nxp-clk): add get_rate for s32cc_fixed_div
feat(nxp-clk): add get_rate for s32cc_dfs_div
feat(nxp-clk): add get_rate for s32cc_dfs
feat(nxp-clk): add get_rate for s32cc_pll
feat(nxp-clk): add get_rate for s32cc_clk
feat(nxp-clk): add a basic get_rate implementation

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fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset

The model has a bug where it will not clear CPUPWRCTLR_EL1 on reset,
even though the actual cores do. The write of 1 to the bit itself
trig

fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset

The model has a bug where it will not clear CPUPWRCTLR_EL1 on reset,
even though the actual cores do. The write of 1 to the bit itself
triggers the powerdown sequnece, regardless of the value before the
write. As such, the bug does not impact functionality but it does throw
off software reading it.

Clear the bit on Travis and Gelas as they are the only ones to require
reading it back.

Change-Id: I765a7fa055733d522480be30d412e3b417af2bd7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(mt8196): refactor LPM header include paths to use lpm_v2

These changes align the project with the latest directory structure
and ensure consistency in header references.

Signed-off-by: Wenzhen

feat(mt8196): refactor LPM header include paths to use lpm_v2

These changes align the project with the latest directory structure
and ensure consistency in header references.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I7f3c42cbd9a803064bbfed67cd8f309638da8441

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refactor(mediatek): update API calls to MTK GIC v3 driver

Updated the code to call the API of MTK GIC v3.

Change-Id: I1bb1771dda4d5532b1b818864f823dbb7a38094d
Signed-off-by: Gavin Liu <gavin.liu@me

refactor(mediatek): update API calls to MTK GIC v3 driver

Updated the code to call the API of MTK GIC v3.

Change-Id: I1bb1771dda4d5532b1b818864f823dbb7a38094d
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(tc): enable Arm SPE for TC4

Enable the Arm SPE DT binding for TC4.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I9ea49046a663eecc2b97ec

feat(tc): enable Arm SPE for TC4

Enable the Arm SPE DT binding for TC4.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I9ea49046a663eecc2b97ecef9ca939575d71fdd9

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feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of B

feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of BL32 is passed via firmware config info.

Add the support to get the address using fconf framework from dynamic
config info.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I3a2a5706789ed290dc7f4a67e62e03751b930c02

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feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32

feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32 image. SP is loaded by SP load framework and configured by
Hafnium.

Add the dts files needed to enable load and configuration of hafnium and
SP.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd

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feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of T

feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of Trusted SRAM. However, for RESET_TO_BL31, the
PLAT_ARM_SPMC_MANIFEST_BASE macro can be used to set it to a different
location which is then used to populate ARM_SPMC_MANIFEST_BASE.

As the RD-V3 platform and its variants have a different SRAM layout
compared to that defined in arm_def.h, define the
PLAT_ARM_SPMC_MANIFEST_BASE macro to an address suitable for this
platform and its variants.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I36e1eb21ab3d1c68bddb52c62198fcdfc40d8993

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