Merge "fix(spmd): prevent SIMD context loss" into integration

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

Change-Id: I23f468a3e5f7daa832c0841b55211a048284a7f0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b9996

feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b99960b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cg

feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cgm_div.freq) will be returned.

Change-Id: I41698990952b530021de26eb51f74aca50176575
Co-developed-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the e

feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the enablement process.

Change-Id: Ide9c8c64be16a66b66f129735cebfc4d1f1772c5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Cha

feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Change-Id: Iadb84f4f47531a67b0b1509b94e1f2b962631a77
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generat

feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generation. In the first case, the request will be propagated to the
parent object of the partition link.

Change-Id: Ic237972008eb51c62e92f03f657698a8a1ca4b0e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(libc): remove __Nonnull type specifier" into integration

fix(rme): map DEVICE0_BASE as EL3_PAS

To pass SMMUv3 Realm Page 0 address to RMM
in Boot Manifest, BL31 needs to read SMMU_ROOT_IDR0
register. BL31 at EL3 runs in Root mode, but
CoreSight and periph

fix(rme): map DEVICE0_BASE as EL3_PAS

To pass SMMUv3 Realm Page 0 address to RMM
in Boot Manifest, BL31 needs to read SMMU_ROOT_IDR0
register. BL31 at EL3 runs in Root mode, but
CoreSight and peripherals at DEVICE0_BASE
(0x2000_0000) including SMMUv3 at 0x2B40_0000 are
mapped as MT_SECURE which results in RAZ access
to all SMMUv3 registers after enabling MMU.
This patch changes MT_SECURE mapping to EL3_PAS
resulting in MT_SECURE (ENABLE_RME = 0), and
MT_ROOT (ENABLE_RME = 1).

Change-Id: I3d9ae7c86e4836dd6722fa64116a14d8c8aed8da
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto

Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional

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fix(versal2): pass tl address to bl32

Pass transfer list address to BL32 as an argument during boot time.

Change-Id: Ic63649b9c41cfae2365ec5911dcab63a7dd005ff
Signed-off-by: Maheedhar Bollapalli <m

fix(versal2): pass tl address to bl32

Pass transfer list address to BL32 as an argument during boot time.

Change-Id: Ic63649b9c41cfae2365ec5911dcab63a7dd005ff
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic d

fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic due to the absence of a console type.
Added fallback option and check for zero base address.

Change-Id: I5f5e0222685ba015ab7db2ecbd46d906f5ab9116
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
o

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.

Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapal

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Si

chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): update transfer list as optional

Updated transfer list feature as optional and user should explicitly
provide build time argument to enable transfer list.
In TL optional case TL addres

fix(versal2): update transfer list as optional

Updated transfer list feature as optional and user should explicitly
provide build time argument to enable transfer list.
In TL optional case TL address range is utilized as default dtb
address range. Updated default DT address to transfer list address.

Change-Id: Ieeaacb3e6fda4ad1da9330708e19d776bffb06c1
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(libc): remove __Nonnull type specifier

Clang's nullability completeness checks were triggered after adding
the _Nonnull specifier to one function. Removing it prevents Clang
from flagging atexit

fix(libc): remove __Nonnull type specifier

Clang's nullability completeness checks were triggered after adding
the _Nonnull specifier to one function. Removing it prevents Clang
from flagging atexit() for missing a nullability specifier.

include/lib/libc/stdlib.h:25:25: error: pointer is missing a
nullability type specifier (_Nonnull, _Nullable, or _Null_unspecified)
[-Werror,-Wnullability-completeness]
25 | extern int atexit(void (*func)(void));

This change ensures compliance with the C standard while preventing
unexpected build errors.

Change-Id: I2f881c55b36b692d22c3db22149c6402c32e8c3e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I3d7a5a92,I5b2d035e into integration

* changes:
fix(mt8196): remove EC_SUSPEND_PIN initial setting
fix(mt8196): remove SPM support for ES chip

Merge "fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31" into integration

Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU c

Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU code in a dedicated file
refactor(tc): add plat_rse_comms_init
refactor(arm)!: rename PLAT_MHU_VERSION flag

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