1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #include <plat_xfer_list.h> 31 #include <pm_api_sys.h> 32 #include <pm_client.h> 33 34 #include <plat_ocm_coherency.h> 35 36 static entry_point_info_t bl32_image_ep_info; 37 static entry_point_info_t bl33_image_ep_info; 38 39 /* 40 * Return a pointer to the 'entry_point_info' structure of the next image for 41 * the security state specified. BL33 corresponds to the non-secure image type 42 * while BL32 corresponds to the secure image type. A NULL pointer is returned 43 * if the image does not exist. 44 */ 45 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 46 { 47 assert(sec_state_is_valid(type)); 48 49 if (type == NON_SECURE) { 50 return &bl33_image_ep_info; 51 } 52 53 return &bl32_image_ep_info; 54 } 55 56 /* 57 * Set the build time defaults,if we can't find any config data. 58 */ 59 static inline void bl31_set_default_config(void) 60 { 61 bl32_image_ep_info.pc = BL32_BASE; 62 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 63 #if defined(SPD_opteed) 64 #if (TRANSFER_LIST == 0) 65 /* NS dtb addr passed to optee_os */ 66 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 67 #endif 68 #endif 69 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 70 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 71 DISABLE_ALL_EXCEPTIONS); 72 } 73 74 /* 75 * Perform any BL31 specific platform actions. Here is an opportunity to copy 76 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 77 * are lost (potentially). This needs to be done before the MMU is initialized 78 * so that the memory layout can be used while creating page tables. 79 */ 80 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 81 u_register_t arg2, u_register_t arg3) 82 { 83 (void)arg0; 84 (void)arg1; 85 (void)arg2; 86 (void)arg3; 87 uint32_t uart_clock; 88 #if (TRANSFER_LIST == 1) 89 int32_t rc; 90 bool tl_status = false; 91 #endif 92 93 board_detection(); 94 95 /* FIXME */ 96 switch (platform_id) { 97 case SPP: 98 switch (platform_version) { 99 case SPP_PSXC_MMI_V2_0: 100 cpu_clock = 770000; 101 break; 102 case SPP_PSXC_MMI_V3_0: 103 cpu_clock = 908000; 104 break; 105 default: 106 panic(); 107 } 108 break; 109 case SPP_MMD: 110 switch (platform_version) { 111 case SPP_PSXC_ISP_AIE_V2_0: 112 case SPP_PSXC_MMD_AIE_FRZ_EA: 113 case SPP_PSXC_MMD_AIE_V3_0: 114 cpu_clock = 760000; 115 break; 116 default: 117 panic(); 118 } 119 break; 120 case EMU: 121 case EMU_MMD: 122 cpu_clock = 112203; 123 break; 124 case QEMU: 125 /* Random values now */ 126 cpu_clock = 3333333; 127 break; 128 case SILICON: 129 cpu_clock = 100000000; 130 break; 131 default: 132 panic(); 133 } 134 #if (TRANSFER_LIST == 1) 135 tl_status = populate_data_from_xfer_list(); 136 if (tl_status != true) { 137 WARN("Invalid transfer list\n"); 138 } 139 #endif 140 141 uart_clock = get_uart_clk(); 142 143 /* Initialize the platform config for future decision making */ 144 config_setup(); 145 146 setup_console(); 147 148 if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) { 149 NOTICE("OCM coherency check not supported\n"); 150 } 151 152 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 153 board_name_decode(), 154 (platform_version >> 1), platform_version % 10U, 155 (rtlversion >> 1), rtlversion % 10U, 156 (psversion >> 1), psversion % 10U, 157 (pmcversion >> 1), pmcversion % 10U); 158 159 /* 160 * Do initial security configuration to allow DRAM/device access. On 161 * Base only DRAM security is programmable (via TrustZone), but 162 * other platforms might have more programmable security devices 163 * present. 164 */ 165 166 /* Populate common information for BL32 and BL33 */ 167 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 168 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 169 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 171 172 #if (TRANSFER_LIST == 1) 173 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 174 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 175 NOTICE("BL31: TL not found, using default config\n"); 176 bl31_set_default_config(); 177 } 178 #else 179 bl31_set_default_config(); 180 #endif 181 182 long rev_var = cpu_get_rev_var(); 183 184 INFO("CPU Revision = 0x%lx\n", rev_var); 185 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 186 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 187 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 188 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 189 190 } 191 192 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 193 194 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 195 { 196 static uint32_t index; 197 uint32_t i; 198 int32_t ret = 0; 199 200 /* Validate 'handler' and 'id' parameters */ 201 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 202 ret = -EINVAL; 203 goto exit_label; 204 } 205 206 /* Check if a handler has already been registered */ 207 for (i = 0; i < index; i++) { 208 if (id == type_el3_interrupt_table[i].id) { 209 ret = -EALREADY; 210 goto exit_label; 211 } 212 } 213 214 type_el3_interrupt_table[index].id = id; 215 type_el3_interrupt_table[index].handler = handler; 216 217 index++; 218 219 exit_label: 220 return ret; 221 } 222 223 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 224 void *handle, void *cookie) 225 { 226 (void)id; 227 uint32_t intr_id; 228 uint32_t i; 229 interrupt_type_handler_t handler = NULL; 230 231 intr_id = plat_ic_get_pending_interrupt_id(); 232 233 for (i = 0; i < MAX_INTR_EL3; i++) { 234 if (intr_id == type_el3_interrupt_table[i].id) { 235 handler = type_el3_interrupt_table[i].handler; 236 } 237 } 238 239 if (handler != NULL) { 240 (void)handler(intr_id, flags, handle, cookie); 241 } 242 243 return 0; 244 } 245 246 void bl31_platform_setup(void) 247 { 248 prepare_dtb(); 249 250 /* Initialize the gic cpu and distributor interfaces */ 251 plat_gic_driver_init(); 252 plat_gic_init(); 253 254 if (platform_id != EMU) { 255 init_scmi_server(); 256 } 257 } 258 259 void bl31_plat_runtime_setup(void) 260 { 261 uint32_t flags = 0; 262 int32_t rc; 263 264 set_interrupt_rm_flag(flags, NON_SECURE); 265 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 266 rdo_el3_interrupt_handler, flags); 267 if (rc != 0) { 268 panic(); 269 } 270 271 console_switch_state(CONSOLE_FLAG_RUNTIME); 272 } 273 274 /* 275 * Perform the very early platform specific architectural setup here. 276 */ 277 void bl31_plat_arch_setup(void) 278 { 279 const mmap_region_t bl_regions[] = { 280 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 281 MT_MEMORY | MT_RW | MT_SECURE), 282 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 283 MT_CODE | MT_SECURE), 284 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 285 MT_RO_DATA | MT_SECURE), 286 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 287 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 288 {0} 289 }; 290 291 setup_page_tables(bl_regions, plat_get_mmap()); 292 enable_mmu(0); 293 } 294