1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/tzc_common.h> 14 #include <lib/bakery_lock.h> 15 #include <lib/cassert.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/gpt_rme/gpt_rme.h> 18 #include <lib/spinlock.h> 19 #include <lib/transfer_list.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 23 /******************************************************************************* 24 * Forward declarations 25 ******************************************************************************/ 26 struct meminfo; 27 struct image_info; 28 struct bl_params; 29 30 typedef struct arm_tzc_regions_info { 31 unsigned long long base; 32 unsigned long long end; 33 unsigned int sec_attr; 34 unsigned int nsaid_permissions; 35 } arm_tzc_regions_info_t; 36 37 typedef struct arm_gpt_info { 38 pas_region_t *pas_region_base; 39 unsigned int pas_region_count; 40 uintptr_t l0_base; 41 uintptr_t l1_base; 42 size_t l0_size; 43 size_t l1_size; 44 gpccr_pps_e pps; 45 gpccr_pgs_e pgs; 46 } arm_gpt_info_t; 47 48 /******************************************************************************* 49 * Default mapping definition of the TrustZone Controller for ARM standard 50 * platforms. 51 * Configure: 52 * - Region 0 with no access; 53 * - Region 1 with secure access only; 54 * - the remaining DRAM regions access from the given Non-Secure masters. 55 ******************************************************************************/ 56 57 #if ENABLE_RME 58 #define ARM_TZC_RME_REGIONS_DEF \ 59 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 60 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 61 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 /* Realm and Shared area share the same PAS */ \ 64 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 67 PLAT_ARM_TZC_NS_DEV_ACCESS} 68 #endif 69 70 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 71 #define ARM_TZC_REGIONS_DEF \ 72 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 73 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 74 {ARM_AP_TZC_DRAM1_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE - 1), \ 75 TZC_REGION_S_RDWR, 0}, \ 76 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 77 PLAT_SP_IMAGE_NS_BUF_SIZE - 1), TZC_REGION_S_NONE, \ 78 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 79 {PLAT_SP_IMAGE_STACK_BASE, ARM_EL3_TZC_DRAM1_END, \ 80 TZC_REGION_S_RDWR, 0}, \ 81 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 82 PLAT_ARM_TZC_NS_DEV_ACCESS} 83 84 #elif ENABLE_RME 85 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 86 MEASURED_BOOT 87 #define ARM_TZC_REGIONS_DEF \ 88 ARM_TZC_RME_REGIONS_DEF, \ 89 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 90 TZC_REGION_S_RDWR, 0} 91 #else 92 #define ARM_TZC_REGIONS_DEF \ 93 ARM_TZC_RME_REGIONS_DEF 94 #endif 95 96 #else 97 #define ARM_TZC_REGIONS_DEF \ 98 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 99 TZC_REGION_S_RDWR, 0}, \ 100 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 101 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 102 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 103 PLAT_ARM_TZC_NS_DEV_ACCESS} 104 #endif 105 106 #define ARM_CASSERT_MMAP \ 107 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 108 assert_plat_arm_mmap_mismatch); \ 109 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 110 <= MAX_MMAP_REGIONS, \ 111 assert_max_mmap_regions); 112 113 void arm_setup_romlib(void); 114 115 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 116 /* 117 * Use this macro to instantiate lock before it is used in below 118 * arm_lock_xxx() macros 119 */ 120 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 121 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 122 123 #if !HW_ASSISTED_COHERENCY 124 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 125 #else 126 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 127 #endif 128 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 129 130 /* 131 * These are wrapper macros to the Coherent Memory Bakery Lock API. 132 */ 133 #define arm_lock_init() bakery_lock_init(&arm_lock) 134 #define arm_lock_get() bakery_lock_get(&arm_lock) 135 #define arm_lock_release() bakery_lock_release(&arm_lock) 136 137 #else 138 139 /* 140 * Empty macros for all other BL stages other than BL31 and BL32 141 */ 142 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 143 #define ARM_LOCK_GET_INSTANCE 0 144 #define arm_lock_init() 145 #define arm_lock_get() 146 #define arm_lock_release() 147 148 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 149 150 #if ARM_RECOM_STATE_ID_ENC 151 /* 152 * Macros used to parse state information from State-ID if it is using the 153 * recommended encoding for State-ID. 154 */ 155 #define ARM_LOCAL_PSTATE_WIDTH 4 156 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 157 158 /* Last in Level for the OS-initiated */ 159 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 160 (ARM_LOCAL_PSTATE_WIDTH * \ 161 (PLAT_MAX_PWR_LVL + 1))) 162 163 /* Macros to construct the composite power state */ 164 165 /* Make composite power state parameter till power level 0 */ 166 #if PSCI_EXTENDED_STATE_ID 167 168 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 169 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 170 #else 171 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 172 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 173 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 174 ((type) << PSTATE_TYPE_SHIFT)) 175 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 176 177 /* Make composite power state parameter till power level 1 */ 178 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 179 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 180 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 181 182 /* Make composite power state parameter till power level 2 */ 183 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 184 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 185 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 186 187 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 188 189 /* ARM State switch error codes */ 190 #define STATE_SW_E_PARAM (-2) 191 #define STATE_SW_E_DENIED (-3) 192 193 /* plat_get_rotpk_info() flags */ 194 #define ARM_ROTPK_REGS_ID 1 195 #define ARM_ROTPK_DEVEL_RSA_ID 2 196 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 197 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 198 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 199 200 #define ARM_USE_DEVEL_ROTPK \ 201 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 202 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 203 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 204 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 205 206 /* IO storage utility functions */ 207 int arm_io_setup(void); 208 209 /* Set image specification in IO block policy */ 210 int arm_set_image_source(unsigned int image_id, const char *part_name, 211 uintptr_t *dev_handle, uintptr_t *image_spec); 212 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 213 214 /* Security utility functions */ 215 void arm_tzc400_setup(uintptr_t tzc_base, 216 const arm_tzc_regions_info_t *tzc_regions); 217 struct tzc_dmc500_driver_data; 218 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 219 const arm_tzc_regions_info_t *tzc_regions); 220 221 /* Console utility functions */ 222 void arm_console_boot_init(void); 223 void arm_console_boot_end(void); 224 void arm_console_runtime_init(void); 225 void arm_console_runtime_end(void); 226 227 /* Systimer utility function */ 228 void arm_configure_sys_timer(void); 229 230 /* PM utility functions */ 231 int arm_validate_power_state(unsigned int power_state, 232 psci_power_state_t *req_state); 233 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 234 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 235 void arm_system_pwr_domain_save(void); 236 void arm_system_pwr_domain_resume(void); 237 int arm_psci_read_mem_protect(int *enabled); 238 int arm_nor_psci_write_mem_protect(int val); 239 void arm_nor_psci_do_static_mem_protect(void); 240 void arm_nor_psci_do_dyn_mem_protect(void); 241 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 242 243 /* Topology utility function */ 244 int arm_check_mpidr(u_register_t mpidr); 245 246 /* BL1 utility functions */ 247 void arm_bl1_early_platform_setup(void); 248 void arm_bl1_platform_setup(void); 249 void arm_bl1_plat_arch_setup(void); 250 251 /* BL2 utility functions */ 252 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 253 u_register_t arg2, u_register_t arg3); 254 void arm_bl2_platform_setup(void); 255 void arm_bl2_plat_arch_setup(void); 256 uint32_t arm_get_spsr_for_bl32_entry(void); 257 uint32_t arm_get_spsr_for_bl33_entry(void); 258 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 259 int arm_bl2_handle_post_image_load(unsigned int image_id); 260 struct bl_params *arm_get_next_bl_params(void); 261 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 262 263 /* BL2 at EL3 functions */ 264 void arm_bl2_el3_early_platform_setup(void); 265 void arm_bl2_el3_plat_arch_setup(void); 266 #if ARM_FW_CONFIG_LOAD_ENABLE 267 void arm_bl2_el3_plat_config_load(void); 268 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */ 269 270 /* BL2U utility functions */ 271 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 272 void *plat_info); 273 void arm_bl2u_platform_setup(void); 274 void arm_bl2u_plat_arch_setup(void); 275 276 /* BL31 utility functions */ 277 #if TRANSFER_LIST 278 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 279 u_register_t arg2, u_register_t arg3); 280 #else 281 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 282 uintptr_t hw_config, void *plat_params_from_bl2); 283 #endif 284 void arm_bl31_platform_setup(void); 285 void arm_bl31_plat_runtime_setup(void); 286 void arm_bl31_plat_arch_setup(void); 287 288 /* Firmware Handoff utility functions */ 289 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 290 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 291 struct transfer_list_header *secure_tl); 292 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 293 struct transfer_list_header *ns_tl); 294 struct transfer_list_entry * 295 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 296 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 297 298 /* TSP utility functions */ 299 void arm_tsp_early_platform_setup(void); 300 301 /* SP_MIN utility functions */ 302 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 303 u_register_t arg2, u_register_t arg3); 304 void arm_sp_min_plat_runtime_setup(void); 305 void arm_sp_min_plat_arch_setup(void); 306 307 /* FIP TOC validity check */ 308 bool arm_io_is_toc_valid(void); 309 310 /* Utility functions for Dynamic Config */ 311 312 void arm_bl1_set_mbedtls_heap(void); 313 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 314 315 #if IMAGE_BL2 316 void arm_bl2_dyn_cfg_init(void); 317 #endif /* IMAGE_BL2 */ 318 319 #if MEASURED_BOOT 320 #if DICE_PROTECTION_ENVIRONMENT 321 int arm_set_nt_fw_info(int *ctx_handle); 322 int arm_set_tb_fw_info(int *ctx_handle); 323 int arm_get_tb_fw_info(int *ctx_handle); 324 #else 325 /* Specific to event log backend */ 326 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 327 int arm_set_nt_fw_info( 328 /* 329 * Currently OP-TEE does not support reading DTBs from Secure memory 330 * and this option should be removed when feature is supported. 331 */ 332 #ifdef SPD_opteed 333 uintptr_t log_addr, 334 #endif 335 size_t log_size, uintptr_t *ns_log_addr); 336 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 337 size_t log_max_size); 338 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 339 size_t *log_max_size); 340 #endif /* DICE_PROTECTION_ENVIRONMENT */ 341 #endif /* MEASURED_BOOT */ 342 343 /* 344 * Free the memory storing initialization code only used during an images boot 345 * time so it can be reclaimed for runtime data 346 */ 347 void arm_free_init_memory(void); 348 349 /* 350 * Make the higher level translation tables read-only 351 */ 352 void arm_xlat_make_tables_readonly(void); 353 354 /* 355 * Mandatory functions required in ARM standard platforms 356 */ 357 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 358 void plat_arm_gic_driver_init(void); 359 void plat_arm_gic_init(void); 360 void plat_arm_gic_cpuif_enable(void); 361 void plat_arm_gic_cpuif_disable(void); 362 void plat_arm_gic_redistif_on(void); 363 void plat_arm_gic_redistif_off(void); 364 void plat_arm_gic_pcpu_init(void); 365 void plat_arm_gic_save(void); 366 void plat_arm_gic_resume(void); 367 void plat_arm_security_setup(void); 368 void plat_arm_pwrc_setup(void); 369 void plat_arm_interconnect_init(void); 370 void plat_arm_interconnect_enter_coherency(void); 371 void plat_arm_interconnect_exit_coherency(void); 372 void plat_arm_program_trusted_mailbox(uintptr_t address); 373 bool plat_arm_bl1_fwu_needed(void); 374 int plat_arm_ni_setup(uintptr_t global_cfg); 375 __dead2 void plat_arm_error_handler(int err); 376 __dead2 void plat_arm_system_reset(void); 377 378 /* 379 * Optional functions in ARM standard platforms 380 */ 381 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 382 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 383 unsigned int *flags); 384 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 385 unsigned int *flags); 386 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 387 unsigned int *flags); 388 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 389 unsigned int *flags); 390 391 #if ARM_PLAT_MT 392 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 393 #endif 394 395 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 396 397 /* 398 * This function is called after loading SCP_BL2 image and it is used to perform 399 * any platform-specific actions required to handle the SCP firmware. 400 */ 401 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 402 403 /* 404 * Optional functions required in ARM standard platforms 405 */ 406 void plat_arm_io_setup(void); 407 int plat_arm_get_alt_image_source( 408 unsigned int image_id, 409 uintptr_t *dev_handle, 410 uintptr_t *image_spec); 411 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 412 const mmap_region_t *plat_arm_get_mmap(void); 413 414 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 415 void arm_gpt_setup(void); 416 417 /* Allow platform to override psci_pm_ops during runtime */ 418 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 419 420 /* Execution state switch in ARM platforms */ 421 int arm_execution_state_switch(unsigned int smc_fid, 422 uint32_t pc_hi, 423 uint32_t pc_lo, 424 uint32_t cookie_hi, 425 uint32_t cookie_lo, 426 void *handle); 427 428 /* Optional functions for SP_MIN */ 429 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 430 u_register_t arg2, u_register_t arg3); 431 432 /* global variables */ 433 extern plat_psci_ops_t plat_arm_psci_pm_ops; 434 extern const mmap_region_t plat_arm_mmap[]; 435 extern const unsigned int arm_pm_idle_states[]; 436 extern struct transfer_list_header *secure_tl; 437 438 /* secure watchdog */ 439 void plat_arm_secure_wdt_start(void); 440 void plat_arm_secure_wdt_stop(void); 441 void plat_arm_secure_wdt_refresh(void); 442 443 /* Get SOC-ID of ARM platform */ 444 uint32_t plat_arm_get_soc_id(void); 445 446 #endif /* PLAT_ARM_H */ 447