Preempt/Resume standard function ID calls

This patch allows servicing of the non-secure world IRQs when the
CPU is in the secure world. Once the interrupt is handled, the
non-secure world issues the

Preempt/Resume standard function ID calls

This patch allows servicing of the non-secure world IRQs when the
CPU is in the secure world. Once the interrupt is handled, the
non-secure world issues the Resume FID to allow the secure payload
complete the preempted standard FID.

Change-Id: Ia52c41adf45014ab51d8447bed6605ca2f935587
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Translate secure/non-secure virtual addresses

This patch adds functionality to translate virtual addresses from
secure or non-secure worlds. This functionality helps Trusted Apps
to share virtual ad

Translate secure/non-secure virtual addresses

This patch adds functionality to translate virtual addresses from
secure or non-secure worlds. This functionality helps Trusted Apps
to share virtual addresses directly and allows the NS world to
pass virtual addresses to TLK directly.

Change-Id: I77b0892963e0e839c448b5d0532920fb7e54dc8e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Register NS shared memory for SP's activity logs and TA sessions

This patch registers NS memory buffer with the secure payload using
two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF.

Register NS shared memory for SP's activity logs and TA sessions

This patch registers NS memory buffer with the secure payload using
two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF.

a. The SP uses the log-buffer to store its activity logs, in a
pre-decided format. This helps in debugging secure payload's issues.
b. The SP uses the req-buffer to get the parameters required by
sessions with Trusted Applications.

Change-Id: I6b0247cf7790524132ee0da24f1f35b1fccec5d5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd)

TLK Dispatcher (tlkd) is based on the tspd and is the glue required
to run TLK as a Secure Payload with the Trusted Firmware.

Change-Id

Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd)

TLK Dispatcher (tlkd) is based on the tspd and is the glue required
to run TLK as a Secure Payload with the Trusted Firmware.

Change-Id: I69e573d26d52342eb049feef773dd7d2a506f4ab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Remove the `owner` field in bakery_lock_t data structure

This patch removes the `owner` field in bakery_lock_t structure which
is the data structure used in the bakery lock implementation that uses

Remove the `owner` field in bakery_lock_t data structure

This patch removes the `owner` field in bakery_lock_t structure which
is the data structure used in the bakery lock implementation that uses
coherent memory. The assertions to protect against recursive lock
acquisition were based on the 'owner' field. They are now done based
on the bakery lock ticket number. These assertions are also added
to the bakery lock implementation that uses normal memory as well.

Change-Id: If4850a00dffd3977e218c0f0a8d145808f36b470

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Optimize the bakery lock structure for coherent memory

This patch optimizes the data structure used with the bakery lock
implementation for coherent memory to save memory and minimize memory
accesse

Optimize the bakery lock structure for coherent memory

This patch optimizes the data structure used with the bakery lock
implementation for coherent memory to save memory and minimize memory
accesses. These optimizations were already part of the bakery lock
implementation for normal memory and this patch now implements
it for the coherent memory implementation as well. Also
included in the patch is a cleanup to use the do-while loop while
waiting for other contenders to finish choosing their tickets.

Change-Id: Iedb305473133dc8f12126726d8329b67888b70f1

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Bug Fix: Fix checkpatch rule in Makefile

The shell command used to list all files but the libc's ones
introduced in commit 95d5353c33 was incorrect. It was listing
subdirectories without referencing

Bug Fix: Fix checkpatch rule in Makefile

The shell command used to list all files but the libc's ones
introduced in commit 95d5353c33 was incorrect. It was listing
subdirectories without referencing their parent directories.
This patch fixes it.

Also, the command used to invoke the checkpatch.pl script is now
printed when V=1.

Change-Id: Ie2f1e74f60d77e38c25e717cffa44ca03baec7b2

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Merge pull request #274 from sandrine-bailleux/sb/juno-r1

Add support for Juno r1 in the platform reset handler

Merge pull request #273 from achingupta/ag/genfw-389

Set group status of PPIs and SGIs correctly on GICv3 systems

Add support for Juno r1 in the platform reset handler

For Juno r0, the platform reset handler needs to:
- Implement the workaround for defect #831273
- Increase the L2 Data and Tag RAM latencies f

Add support for Juno r1 in the platform reset handler

For Juno r0, the platform reset handler needs to:
- Implement the workaround for defect #831273
- Increase the L2 Data and Tag RAM latencies for Cortex-A57.

Defect #831273 does not affect Juno r1. Also, the default value
for the L2 Tag RAM latency for Cortex-A57 is suitable on Juno r1.
The L2 Data RAM latency for Cortex-A57 still needs to be
increased, though.

This patch modifies the Juno platform reset handler to detect
the board revision and skip the unnecessary steps on Juno r1.
The behaviour on Juno r0 is unchanged.

Change-Id: I27542917223e680ef923ee860900806ffcd0357b

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Set group status of PPIs and SGIs correctly on GICv3 systems

On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0
register. On a GICv3 system, if affinity routing is enab

Set group status of PPIs and SGIs correctly on GICv3 systems

On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0
register. On a GICv3 system, if affinity routing is enabled for the non-secure
state, then the group status of PPIs and SGIs should be set in the GICR_IGROUPR0
register. ARM Trusted firmware sets the group status using the GICv2
sequence. On a GICv3 system, if the group status of an interrupt is set to Group
1 through a write to the GICD_IGROUPR0, then the GICR_IGROUPR0 is updated as
well.

The current sequence is incorrect since it first marks all PPIs and SGIs as
Group 1. It then clears the bits in GICD_IGROUPR0 corresponding to secure
interrupts to set their group status to Group 0. This operation is a no-op. It
leaves the secure generic timer interrupt (#29) used by the TSP marked as Group
1. This causes the interrupt to interfere with the execution of non-secure
software. Once an interrupt has been marked as Group 1, the GICR_IGROUPR0 should
be programmed to change its group status.

This patch rectifies this issue by setting the group status of only the
non-secure PPI and SGIs to Group 1 in the first place. GICD_IGROUPR0 resets to
0. So secure interrupts are marked as Group 0 by default.

Change-Id: I958b4b15f3e2b2444ce4c17764def36216498d00

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Merge pull request #270 from vikramkanigiri/vk/a72_cpu_support

Add support for ARM Cortex-A72 processor

Add support for ARM Cortex-A72 processor

This patch adds support for ARM Cortex-A72 processor in the CPU
specific framework.

Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175

Merge pull request #263 from jcastillo-arm/jc/tbb_sha256_int

TBB: remove PolarSSL SHA1 functions from the binary

Merge pull request #269 from vikramkanigiri/vk/common-cci

Common driver for ARM cache coherent Interconnects

Merge pull request #268 from vikramkanigiri/vk/move_init_cpu_ops

Initialise cpu ops after enabling data cache

Merge pull request #267 from sandrine-bailleux/sb/doc-fixes

Documentation fixes in 'make help' message and User Guide

Merge pull request #266 from sandrine-bailleux/sb/juno-disable-errata-806969

Juno: Disable workaround for Cortex-A57 erratum #806969

Merge pull request #264 from jcastillo-arm/jc/tbb_fip_dep

TBB: fix build target 'all' dependency on certificates

Merge pull request #262 from sandrine-bailleux/sb/check-format-printf

Enable type-checking of arguments passed to printf() et al.

Merge pull request #265 from jcastillo-arm/jc/git_commit_id

checkpatch: ignore GIT_COMMIT_ID

Use ARM CCI driver on FVP and Juno platforms

This patch updates the FVP and Juno platform ports to use the common
driver for ARM Cache Coherent Interconnects.

Change-Id: Ib142f456b9b673600592616a2e

Use ARM CCI driver on FVP and Juno platforms

This patch updates the FVP and Juno platform ports to use the common
driver for ARM Cache Coherent Interconnects.

Change-Id: Ib142f456b9b673600592616a2ec99e9b230d6542

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Common driver for ARM Cache Coherent Interconnects

Even though both CCI-400 and CCI-500 IPs have different configurations
with respect to the number and types of supported interfaces, their
register

Common driver for ARM Cache Coherent Interconnects

Even though both CCI-400 and CCI-500 IPs have different configurations
with respect to the number and types of supported interfaces, their
register offsets and programming sequences are similar. This patch
creates a common driver for enabling and disabling snoop transactions
and DVMs with both the IPs.

New platform ports which implement one of these IPs should use this
common driver. Existing platform ports which implement CCI-400 should
migrate to the common driver as the standalone CCI-400 will be
deprecated in the future.

Change-Id: I3ccd0eb7b062922d2e4a374ff8c21e79fa357556

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Add macro to calculate number of elements in an array

This patch defines the ARRAY_SIZE macro for calculating number of elements
in an array and uses it where appropriate.

Change-Id: I72746a9229f0b

Add macro to calculate number of elements in an array

This patch defines the ARRAY_SIZE macro for calculating number of elements
in an array and uses it where appropriate.

Change-Id: I72746a9229f0b259323972b498b9a3999731bc9b

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Initialise cpu ops after enabling data cache

The cpu-ops pointer was initialized before enabling the data cache in the cold
and warm boot paths. This required a DCIVAC cache maintenance operation to

Initialise cpu ops after enabling data cache

The cpu-ops pointer was initialized before enabling the data cache in the cold
and warm boot paths. This required a DCIVAC cache maintenance operation to
invalidate any stale cache lines resident in other cpus.

This patch moves this initialization to the bl31_arch_setup() function
which is always called after the data cache and MMU has been enabled.

This change removes the need:
1. for the DCIVAC cache maintenance operation.
2. to initialise the CPU ops upon resumption from a PSCI CPU_SUSPEND
call since memory contents are always preserved in this case.

Change-Id: Ibb2fa2f7460d1a1f1e721242025e382734c204c6

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