1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <auth_mod.h> 35 #include <bl_common.h> 36 #include <debug.h> 37 #include <platform.h> 38 #include <platform_def.h> 39 #include "bl1_private.h" 40 41 /******************************************************************************* 42 * Runs BL2 from the given entry point. It results in dropping the 43 * exception level 44 ******************************************************************************/ 45 static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) 46 { 47 /* Check bl2 security state is expected as secure */ 48 assert(GET_SECURITY_STATE(bl2_ep->h.attr) == SECURE); 49 /* Check NS Bit is also set as secure */ 50 assert(!(read_scr_el3() & SCR_NS_BIT)); 51 52 bl1_arch_next_el_setup(); 53 54 /* Tell next EL what we want done */ 55 bl2_ep->args.arg0 = RUN_IMAGE; 56 57 write_spsr_el3(bl2_ep->spsr); 58 write_elr_el3(bl2_ep->pc); 59 60 NOTICE("BL1: Booting BL2\n"); 61 print_entry_point_info(bl2_ep); 62 63 eret(bl2_ep->args.arg0, 64 bl2_ep->args.arg1, 65 bl2_ep->args.arg2, 66 bl2_ep->args.arg3, 67 bl2_ep->args.arg4, 68 bl2_ep->args.arg5, 69 bl2_ep->args.arg6, 70 bl2_ep->args.arg7); 71 } 72 73 /******************************************************************************* 74 * The next function has a weak definition. Platform specific code can override 75 * it if it wishes to. 76 ******************************************************************************/ 77 #pragma weak bl1_init_bl2_mem_layout 78 79 /******************************************************************************* 80 * Function that takes a memory layout into which BL2 has been loaded and 81 * populates a new memory layout for BL2 that ensures that BL1's data sections 82 * resident in secure RAM are not visible to BL2. 83 ******************************************************************************/ 84 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 85 meminfo_t *bl2_mem_layout) 86 { 87 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 88 89 assert(bl1_mem_layout != NULL); 90 assert(bl2_mem_layout != NULL); 91 92 /* Check that BL1's memory is lying outside of the free memory */ 93 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || 94 (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); 95 96 /* Remove BL1 RW data from the scope of memory visible to BL2 */ 97 *bl2_mem_layout = *bl1_mem_layout; 98 reserve_mem(&bl2_mem_layout->total_base, 99 &bl2_mem_layout->total_size, 100 BL1_RAM_BASE, 101 bl1_size); 102 103 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 104 } 105 106 /******************************************************************************* 107 * Function to perform late architectural and platform specific initialization. 108 * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only 109 * called by the primary cpu after a cold boot. 110 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 111 * loader etc. 112 ******************************************************************************/ 113 void bl1_main(void) 114 { 115 /* Announce our arrival */ 116 NOTICE(FIRMWARE_WELCOME_STR); 117 NOTICE("BL1: %s\n", version_string); 118 NOTICE("BL1: %s\n", build_message); 119 120 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); 121 122 image_info_t bl2_image_info = { {0} }; 123 entry_point_info_t bl2_ep = { {0} }; 124 meminfo_t *bl1_tzram_layout; 125 meminfo_t *bl2_tzram_layout = 0x0; 126 int err; 127 128 #if DEBUG 129 unsigned long val; 130 /* 131 * Ensure that MMU/Caches and coherency are turned on 132 */ 133 val = read_sctlr_el3(); 134 assert(val & SCTLR_M_BIT); 135 assert(val & SCTLR_C_BIT); 136 assert(val & SCTLR_I_BIT); 137 /* 138 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 139 * provided platform value 140 */ 141 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 142 /* 143 * If CWG is zero, then no CWG information is available but we can 144 * at least check the platform value is less than the architectural 145 * maximum. 146 */ 147 if (val != 0) 148 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 149 else 150 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 151 #endif 152 153 /* Perform remaining generic architectural setup from EL3 */ 154 bl1_arch_setup(); 155 156 /* Perform platform setup in BL1. */ 157 bl1_platform_setup(); 158 159 SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); 160 SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); 161 162 /* Find out how much free trusted ram remains after BL1 load */ 163 bl1_tzram_layout = bl1_plat_sec_mem_layout(); 164 165 INFO("BL1: Loading BL2\n"); 166 167 #if TRUSTED_BOARD_BOOT 168 /* Initialize authentication module */ 169 auth_mod_init(); 170 #endif /* TRUSTED_BOARD_BOOT */ 171 172 /* Load the BL2 image */ 173 err = load_auth_image(bl1_tzram_layout, 174 BL2_IMAGE_ID, 175 BL2_BASE, 176 &bl2_image_info, 177 &bl2_ep); 178 179 if (err) { 180 ERROR("Failed to load BL2 firmware.\n"); 181 plat_error_handler(err); 182 } 183 184 /* 185 * Create a new layout of memory for BL2 as seen by BL1 i.e. 186 * tell it the amount of total and free memory available. 187 * This layout is created at the first free address visible 188 * to BL2. BL2 will read the memory layout before using its 189 * memory for other purposes. 190 */ 191 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; 192 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); 193 194 bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); 195 bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; 196 bl1_run_bl2(&bl2_ep); 197 198 return; 199 } 200 201 /******************************************************************************* 202 * Function called just before handing over to BL31 to inform the user about 203 * the boot progress. In debug mode, also print details about the BL31 image's 204 * execution context. 205 ******************************************************************************/ 206 void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info) 207 { 208 NOTICE("BL1: Booting BL3-1\n"); 209 print_entry_point_info(bl31_ep_info); 210 } 211 212 #if SPIN_ON_BL1_EXIT 213 void print_debug_loop_message(void) 214 { 215 NOTICE("BL1: Debug loop, spinning forever\n"); 216 NOTICE("BL1: Please connect the debugger to continue\n"); 217 } 218 #endif 219