Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): worka

Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): workaround for Neoverse-N2 erratum 3888123
refactor(cpus): reorder the errratum build flag for Neoverse-N2

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Merge changes from topic "xl/cortex-x3-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 4302966
fix(cpus): workaround for Cortex-X3 erratum 3888125

Merge changes from topic "xl/cortex-x2-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 4302969
fix(cpus): workaround for Cortex-X2 erratum 3888122

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a s

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a specific instruction
sequence when disabling the hardware prefetcher.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: Ie465328e87754a1ec511a2f77243b4b0b09134cc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I2436b11a36be204d549522f1176fcd49658c044c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] t

fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I6240d263fb5d153721b5b84a37df2f24e3d02d86
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c0251

refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c02512519782
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(spm-mm): fix wrong range of SPM_MM" into integration

Merge changes I411af9d1,I89813759 into integration

* changes:
feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry
refactor(el3-runtime): factor out handler

Merge changes I411af9d1,I89813759 into integration

* changes:
feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry
refactor(el3-runtime): factor out handler fetching code

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fix(rcar3): prevent boot CPU hot unplug

The boot CPU runs both TFA and later also Trusted OS, which is UP and can
not be migrated to another CPU. Report MIGRATE_INFO_TYPE "Uniprocessor (UP)
not migr

fix(rcar3): prevent boot CPU hot unplug

The boot CPU runs both TFA and later also Trusted OS, which is UP and can
not be migrated to another CPU. Report MIGRATE_INFO_TYPE "Uniprocessor (UP)
not migrate capable 1" to the OS, so any attempts at CPU_OFF and MIGRATE
of the boot CPU would be DENIED. This has an effect also e.g. on the Linux
kernel, where it prevents stopping boot CPU (CPU0) using CPU hotplug, which
must not be allowed, as it would interfere with the Trusted OS.

Change-Id: I0f38e64711c13ae48e819fb33939451720749c68
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

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Merge "feat(rcar3): rephrase RCAR_BL31_CRASH_BASE definition" into integration

Merge "fix(rcar): enable intialisation code for EL3 to NS-EL1 handoff" into integration

fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1

fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I284ee7fe611c4c9861696fde62f796e6fae6dff6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting

fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I5c01dfcffc6e56163aba03428e21fedee8cc7042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(psci): set requested local power states in failure path" into integration

Merge changes I7af8857d,I7fc84d2c into integration

* changes:
docs(maintainers): add Gabriel as clock framework maintainer
docs(maintainers): sort frameworks alphabetically

Merge "feat(mt8196): add audio SMC cmd implementation" into integration

Merge "docs(per-cpu): update diagram for NUMA enabled per-cpu layout" into integration

Merge "build(changelog): add new scope for TI k3low" into integration

Merge "feat(docs): document PSCI power_state" into integration

fix(context-mgmt): actually clear MDCR_EL3 bits

When setting up MDCR_EL3 for a given context, we need to set some bits,
but also clear some other bits. This was done in a single statement,
but using

fix(context-mgmt): actually clear MDCR_EL3 bits

When setting up MDCR_EL3 for a given context, we need to set some bits,
but also clear some other bits. This was done in a single statement,
but using the C "|=" operator, which would never clear any bits in the
left-hand side.

Split this into two statements, one for setting, the other for clearing
bits.

It seems that on the FVP the bits to clear already reset to 0, so this
never caused any issues so far, but the architecture declares those bits
as: "this field resets to an architecturally UNKNOWN value".

Change-Id: Id1e9e4c010167af2ea3d5820532704220aa7c647
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs: update Ignored Checkpatch Warnings chapter" into integration

feat(st): allow the use of clang as linker

Use same .map file structure for llvm-clang and llvm-lld.

Change-Id: I4a3dd76df29e4a38ed33c2bc2c8bbdf31b8d5281
Signed-off-by: Yann Gautier <yann.gautier@s

feat(st): allow the use of clang as linker

Use same .map file structure for llvm-clang and llvm-lld.

Change-Id: I4a3dd76df29e4a38ed33c2bc2c8bbdf31b8d5281
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st): simplify rule to build .stm32 file

Instead of using substitution for STM32_TF_ELF_LDFLAGS, directly use
ld_prefix helper.
Use TF_LDFLAGS to avoid adding -nostartfiles and -no-pie optio

refactor(st): simplify rule to build .stm32 file

Instead of using substitution for STM32_TF_ELF_LDFLAGS, directly use
ld_prefix helper.
Use TF_LDFLAGS to avoid adding -nostartfiles and -no-pie options.
Add -static to STM32_TF_ELF_LDFLAGS options, and --build-id=none is
already handled with TF_LDFLAGS.

Change-Id: I6d64b524d98701007aabf150b5c8229799e663d3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "fix(intel): restore overlap-safe memcpy_s to prevent SoCFPGA BL2 hang" into integration