Merge pull request #687 from sandrine-bailleux-arm/sb/panic-handler

Add WFI in platform's unexpected error handlers

Add WFI in platform's unexpected error handlers

This patch adds a WFI instruction in the default implementations of
plat_error_handler() and plat_panic_handler(). This potentially reduces
power cons

Add WFI in platform's unexpected error handlers

This patch adds a WFI instruction in the default implementations of
plat_error_handler() and plat_panic_handler(). This potentially reduces
power consumption by allowing the hardware to enter a low-power state.
The same change has been made to the FVP and Juno platform ports.

Change-Id: Ia4e6e1e5bf1ed42efbba7d0ebbad7be8d5f9f173

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Merge pull request #686 from danh-arm/dh/remove-inv-dcache-after-auth

Remove dcache invalidation after image authentication

Merge pull request #678 from soby-mathew/sm/PSCI_AArch32

Introduce AArch32 support for PSCI library

Remove dcache invalidation after image authentication

At the end of successful image authentication in load_auth_image(),
the data cache for the virtual address range corresponding to the
image is i

Remove dcache invalidation after image authentication

At the end of successful image authentication in load_auth_image(),
the data cache for the virtual address range corresponding to the
image is invalidated (by a call to inv_dcache_range()). The intent
seems to be to ensure the data caches do not contain any sensitive
data used during authentication, which subsequent code can read.
However, this same address range is already flushed (cleaned and
invalidated by a call to flush_dcache_range()) at the end of
load_image(), and the subsequent invalidate has no functional
effect.

This patch removes the redundant call to inv_dcache_range(). It
also moves the flush_dcache_range() call from the end of load_image()
to the end of load_auth_image(), so the image data will remain in
the caches during authentication, improving performance.

This also improves the comments that explain the rationale for
calling flush_dcache_range() after image loading/authentication.

Change-Id: I14f17ad2935075ef6f3d1327361c5088bfb2d284

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Merge pull request #685 from sandrine-bailleux-arm/sb/base-fvp-7.6

Move up to Base FVP version 7.6

Merge pull request #683 from dp-arm/dp/fiptool

fiptool: Suppress verbose messages during normal build

Merge pull request #682 from sudeep-holla/gicv3_ns_intr

gicv3: disable Group1 NonSecure interrupts during core powerdown

Merge pull request #680 from hzhuang1/emmc_cmd23_v2

emmc: support CMD23

Move up to Base FVP version 7.6

This patch updates the User Guide to move up from version 7.2 to 7.6
of the Base FVP.

Change-Id: I792b2250deb4836266e14b40992ae59a5ab5f729

fiptool: Suppress verbose messages during normal build

The output is shown only when built with V=1.

Change-Id: I17fef10df6f127f07956a78b478ff3cadba4bd61

AArch32: Enable build at top level Makefile for FVP

This patch enables the AArch32 build including SP_MIN in the
top level Makefile. The build flag `ARCH` now can specify either
`aarch64`(default) o

AArch32: Enable build at top level Makefile for FVP

This patch enables the AArch32 build including SP_MIN in the
top level Makefile. The build flag `ARCH` now can specify either
`aarch64`(default) or `aarch32`. Currently only FVP AEM model is
supported for AArch32 build. Another new build flag `AARCH32_SP`
is introduced to specify the AArch32 secure payload to be built.

Change-Id: Ie1198cb9e52d7da1b79b93243338fc3868b08faa

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Merge pull request #679 from rockchip-linux/support-pwm-for-rk3399

Support pwm for rk3399

emmc: support CMD23

Support CMD23. When CMD23 is used, CMD12 could be avoided.

Two scenarios:
1. CMD17 for single block, CMD18 + CMD12 for multiple blocks.
2. CMD23 + CMD18 for both single block an

emmc: support CMD23

Support CMD23. When CMD23 is used, CMD12 could be avoided.

Two scenarios:
1. CMD17 for single block, CMD18 + CMD12 for multiple blocks.
2. CMD23 + CMD18 for both single block and multiple blocks.

The emmc_init() should initialize whether CMD23 is supported
or not.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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gicv3: disable Group1 NonSecure interrupts during core powerdown

As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a

gicv3: disable Group1 NonSecure interrupts during core powerdown

As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a processor,
software must set Enable to zero for all interrupt groups(by writing to
GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.

Also, NonSecure EL1 software may not be aware of the CPU power state
details and fail to choose right states that require quiescing the CPU
interface. So it's preferred that the PSCI implementation handles it as
it is fully aware of the CPU power states.

This patch adds disabling of Group1 NonSecure interrupts during processor
power down along with Group0 and Group1 Secure interrupts so that all the
interrupt groups are handled at once as per specification.

Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641

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rockchip: fix the reset-hold release for rk3399 resume

The pmusgrf reset-hold bits needs to be released, since the
pmusgrf reset-hold bits needs to be held.

Change-Id: Ia1eccc8fba18294f26b4cc07d47b

rockchip: fix the reset-hold release for rk3399 resume

The pmusgrf reset-hold bits needs to be released, since the
pmusgrf reset-hold bits needs to be held.

Change-Id: Ia1eccc8fba18294f26b4cc07d47bc5e513dd9a1f

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rockchip: fix the power up/dowm cnt for rk3399

Sometimes this will cause the long delay for suspend/resume.
Since the 24M OCS will be turned off in power mode.
Also, remove the ERROR_DEPRECATED conf

rockchip: fix the power up/dowm cnt for rk3399

Sometimes this will cause the long delay for suspend/resume.
Since the 24M OCS will be turned off in power mode.
Also, remove the ERROR_DEPRECATED config define.

Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a

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rockchip: update to handle PWMs for rk3399

This patch updates some things for rk3399, as following:

1) Add the new file to handle the pwm. (e.g. the pwm regulator)
Make sure that good deal with the

rockchip: update to handle PWMs for rk3399

This patch updates some things for rk3399, as following:

1) Add the new file to handle the pwm. (e.g. the pwm regulator)
Make sure that good deal with the pwm related things.
Also, remove some pwm setting for pmu.c.

2) Set the plls slow mode and bypass in suspend, and restore them.

Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264

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AArch32: Add FVP support for SP_MIN

This patch implements the support for SP_MIN in FVP. The SP_MIN platform
APIs are implemented and the required makefile support is added for FVP.

Change-Id: Id50

AArch32: Add FVP support for SP_MIN

This patch implements the support for SP_MIN in FVP. The SP_MIN platform
APIs are implemented and the required makefile support is added for FVP.

Change-Id: Id50bd6093eccbd5e38894e3fd2b20d5baeac5452

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AArch32: Add essential ARM platform and FVP support

This patch adds AArch32 support for FVP and implements common platform APIs
like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for

AArch32: Add essential ARM platform and FVP support

This patch adds AArch32 support for FVP and implements common platform APIs
like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for AArch32.
Only Multi Processor(MP) implementations of these functions are considered in
this patch. The ARM Standard platform layer helpers are implemented for
AArch32 and the common makefiles are modified to cater for both AArch64 and
AArch32 builds. Compatibility with the deprecated platform API is not
supported for AArch32.

Change-Id: Iad228400613eec91abf731b49e21a15bcf2833ea

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AArch32: add a minimal secure payload (SP_MIN)

This patch adds a minimal AArch32 secure payload SP_MIN. It relies on PSCI
library to initialize the normal world context. It runs in Monitor mode
and

AArch32: add a minimal secure payload (SP_MIN)

This patch adds a minimal AArch32 secure payload SP_MIN. It relies on PSCI
library to initialize the normal world context. It runs in Monitor mode
and uses the runtime service framework to handle SMCs. It is added as
a BL32 component in the Trusted Firmware source tree.

Change-Id: Icc04fa6b242025a769c1f6c7022fde19459c43e9

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AArch32: Add support to PSCI lib

This patch adds AArch32 support to PSCI library, as follows :

* The `psci_helpers.S` is implemented for AArch32.

* AArch32 version of internal helper function `psc

AArch32: Add support to PSCI lib

This patch adds AArch32 support to PSCI library, as follows :

* The `psci_helpers.S` is implemented for AArch32.

* AArch32 version of internal helper function `psci_get_ns_ep_info()` is
defined.

* The PSCI Library is responsible for the Non Secure context initialization.
Hence a library interface `psci_prepare_next_non_secure_ctx()` is introduced
to enable EL3 runtime firmware to initialize the non secure context without
invoking context management library APIs.

Change-Id: I25595b0cc2dbfdf39dbf7c589b875cba33317b9d

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AArch32: Add support in TF libraries

This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support f

AArch32: Add support in TF libraries

This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support for AArch32 register
arguments. The CPU operations for AEM generic cpu in AArch32
mode is also added.

Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483

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AArch32: Add console driver

This patch adds console drivers including the pl011 driver
for the AArch32 mode.

Change-Id: Ifd22520d370fca3e73dbbf6f2d97d6aee65b67dd

AArch32: Enable GIC and TZC support

This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes t

AArch32: Enable GIC and TZC support

This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.

Note: The legacy GICv3 driver is not supported for AArch32.

Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458

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