1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <platform.h> 36 #include <pmf.h> 37 #include <runtime_instr.h> 38 #include <string.h> 39 #include "psci_private.h" 40 41 /****************************************************************************** 42 * Construct the psci_power_state to request power OFF at all power levels. 43 ******************************************************************************/ 44 static void psci_set_power_off_state(psci_power_state_t *state_info) 45 { 46 int lvl; 47 48 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) 49 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; 50 } 51 52 /****************************************************************************** 53 * Top level handler which is called when a cpu wants to power itself down. 54 * It's assumed that along with turning the cpu power domain off, power 55 * domains at higher levels will be turned off as far as possible. It finds 56 * the highest level where a domain has to be powered off by traversing the 57 * node information and then performs generic, architectural, platform setup 58 * and state management required to turn OFF that power domain and domains 59 * below it. e.g. For a cpu that's to be powered OFF, it could mean programming 60 * the power controller whereas for a cluster that's to be powered off, it will 61 * call the platform specific code which will disable coherency at the 62 * interconnect level if the cpu is the last in the cluster and also the 63 * program the power controller. 64 ******************************************************************************/ 65 int psci_do_cpu_off(unsigned int end_pwrlvl) 66 { 67 int rc = PSCI_E_SUCCESS, idx = plat_my_core_pos(); 68 psci_power_state_t state_info; 69 70 /* 71 * This function must only be called on platforms where the 72 * CPU_OFF platform hooks have been implemented. 73 */ 74 assert(psci_plat_pm_ops->pwr_domain_off); 75 76 /* 77 * This function acquires the lock corresponding to each power 78 * level so that by the time all locks are taken, the system topology 79 * is snapshot and state management can be done safely. 80 */ 81 psci_acquire_pwr_domain_locks(end_pwrlvl, 82 idx); 83 84 /* 85 * Call the cpu off handler registered by the Secure Payload Dispatcher 86 * to let it do any bookkeeping. Assume that the SPD always reports an 87 * E_DENIED error if SP refuse to power down 88 */ 89 if (psci_spd_pm && psci_spd_pm->svc_off) { 90 rc = psci_spd_pm->svc_off(0); 91 if (rc) 92 goto exit; 93 } 94 95 /* Construct the psci_power_state for CPU_OFF */ 96 psci_set_power_off_state(&state_info); 97 98 /* 99 * This function is passed the requested state info and 100 * it returns the negotiated state info for each power level upto 101 * the end level specified. 102 */ 103 psci_do_state_coordination(end_pwrlvl, &state_info); 104 105 #if ENABLE_PSCI_STAT 106 /* Update the last cpu for each level till end_pwrlvl */ 107 psci_stats_update_pwr_down(end_pwrlvl, &state_info); 108 #endif 109 110 #if ENABLE_RUNTIME_INSTRUMENTATION 111 112 /* 113 * Flush cache line so that even if CPU power down happens 114 * the timestamp update is reflected in memory. 115 */ 116 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 117 RT_INSTR_ENTER_CFLUSH, 118 PMF_CACHE_MAINT); 119 #endif 120 121 /* 122 * Arch. management. Perform the necessary steps to flush all 123 * cpu caches. 124 */ 125 psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(&state_info)); 126 127 #if ENABLE_RUNTIME_INSTRUMENTATION 128 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 129 RT_INSTR_EXIT_CFLUSH, 130 PMF_NO_CACHE_MAINT); 131 #endif 132 133 /* 134 * Plat. management: Perform platform specific actions to turn this 135 * cpu off e.g. exit cpu coherency, program the power controller etc. 136 */ 137 psci_plat_pm_ops->pwr_domain_off(&state_info); 138 139 #if ENABLE_PSCI_STAT 140 /* 141 * Capture time-stamp while entering low power state. 142 * No cache maintenance needed because caches are off 143 * and writes are direct to main memory. 144 */ 145 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 146 PMF_NO_CACHE_MAINT); 147 #endif 148 149 exit: 150 /* 151 * Release the locks corresponding to each power level in the 152 * reverse order to which they were acquired. 153 */ 154 psci_release_pwr_domain_locks(end_pwrlvl, 155 idx); 156 157 /* 158 * Check if all actions needed to safely power down this cpu have 159 * successfully completed. 160 */ 161 if (rc == PSCI_E_SUCCESS) { 162 /* 163 * Set the affinity info state to OFF. This writes directly to 164 * main memory as caches are disabled, so cache maintenance is 165 * required to ensure that later cached reads of aff_info_state 166 * return AFF_STATE_OFF. A dsbish() ensures ordering of the 167 * update to the affinity info state prior to cache line 168 * invalidation. 169 */ 170 flush_cpu_data(psci_svc_cpu_data.aff_info_state); 171 psci_set_aff_info_state(AFF_STATE_OFF); 172 dsbish(); 173 inv_cpu_data(psci_svc_cpu_data.aff_info_state); 174 175 #if ENABLE_RUNTIME_INSTRUMENTATION 176 177 /* 178 * Update the timestamp with cache off. We assume this 179 * timestamp can only be read from the current CPU and the 180 * timestamp cache line will be flushed before return to 181 * normal world on wakeup. 182 */ 183 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 184 RT_INSTR_ENTER_HW_LOW_PWR, 185 PMF_NO_CACHE_MAINT); 186 #endif 187 188 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) { 189 /* This function must not return */ 190 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info); 191 } else { 192 /* 193 * Enter a wfi loop which will allow the power 194 * controller to physically power down this cpu. 195 */ 196 psci_power_down_wfi(); 197 } 198 } 199 200 return rc; 201 } 202