1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <platform_def.h> 34#include <psci.h> 35 36 .globl psci_do_pwrdown_cache_maintenance 37 .globl psci_do_pwrup_cache_maintenance 38 .globl psci_power_down_wfi 39#if !ERROR_DEPRECATED 40 .globl psci_entrypoint 41#endif 42 43/* ----------------------------------------------------------------------- 44 * void psci_do_pwrdown_cache_maintenance(unsigned int power level); 45 * 46 * This function performs cache maintenance for the specified power 47 * level. The levels of cache affected are determined by the power 48 * level which is passed as the argument i.e. level 0 results 49 * in a flush of the L1 cache. Both the L1 and L2 caches are flushed 50 * for a higher power level. 51 * 52 * Additionally, this function also ensures that stack memory is correctly 53 * flushed out to avoid coherency issues due to a change in its memory 54 * attributes after the data cache is disabled. 55 * ----------------------------------------------------------------------- 56 */ 57func psci_do_pwrdown_cache_maintenance 58 stp x29, x30, [sp,#-16]! 59 stp x19, x20, [sp,#-16]! 60 61 /* --------------------------------------------- 62 * Invoke CPU-specific power down operations for 63 * the appropriate level 64 * --------------------------------------------- 65 */ 66 bl prepare_cpu_pwr_dwn 67 68 /* --------------------------------------------- 69 * Do stack maintenance by flushing the used 70 * stack to the main memory and invalidating the 71 * remainder. 72 * --------------------------------------------- 73 */ 74 bl plat_get_my_stack 75 76 /* --------------------------------------------- 77 * Calculate and store the size of the used 78 * stack memory in x1. 79 * --------------------------------------------- 80 */ 81 mov x19, x0 82 mov x1, sp 83 sub x1, x0, x1 84 mov x0, sp 85 bl flush_dcache_range 86 87 /* --------------------------------------------- 88 * Calculate and store the size of the unused 89 * stack memory in x1. Calculate and store the 90 * stack base address in x0. 91 * --------------------------------------------- 92 */ 93 sub x0, x19, #PLATFORM_STACK_SIZE 94 sub x1, sp, x0 95 bl inv_dcache_range 96 97 ldp x19, x20, [sp], #16 98 ldp x29, x30, [sp], #16 99 ret 100endfunc psci_do_pwrdown_cache_maintenance 101 102 103/* ----------------------------------------------------------------------- 104 * void psci_do_pwrup_cache_maintenance(void); 105 * 106 * This function performs cache maintenance after this cpu is powered up. 107 * Currently, this involves managing the used stack memory before turning 108 * on the data cache. 109 * ----------------------------------------------------------------------- 110 */ 111func psci_do_pwrup_cache_maintenance 112 stp x29, x30, [sp,#-16]! 113 114 /* --------------------------------------------- 115 * Ensure any inflight stack writes have made it 116 * to main memory. 117 * --------------------------------------------- 118 */ 119 dmb st 120 121 /* --------------------------------------------- 122 * Calculate and store the size of the used 123 * stack memory in x1. Calculate and store the 124 * stack base address in x0. 125 * --------------------------------------------- 126 */ 127 bl plat_get_my_stack 128 mov x1, sp 129 sub x1, x0, x1 130 mov x0, sp 131 bl inv_dcache_range 132 133 /* --------------------------------------------- 134 * Enable the data cache. 135 * --------------------------------------------- 136 */ 137 mrs x0, sctlr_el3 138 orr x0, x0, #SCTLR_C_BIT 139 msr sctlr_el3, x0 140 isb 141 142 ldp x29, x30, [sp], #16 143 ret 144endfunc psci_do_pwrup_cache_maintenance 145 146/* ----------------------------------------------------------------------- 147 * void psci_power_down_wfi(void); 148 * This function is called to indicate to the power controller that it 149 * is safe to power down this cpu. It should not exit the wfi and will 150 * be released from reset upon power up. 151 * ----------------------------------------------------------------------- 152 */ 153func psci_power_down_wfi 154 dsb sy // ensure write buffer empty 155 wfi 156 no_ret plat_panic_handler 157endfunc psci_power_down_wfi 158 159/* ----------------------------------------------------------------------- 160 * void psci_entrypoint(void); 161 * The deprecated entry point for PSCI on warm boot for AArch64. 162 * ----------------------------------------------------------------------- 163 */ 164func_deprecated psci_entrypoint 165 b bl31_warm_entrypoint 166endfunc_deprecated psci_entrypoint 167