fix(rd1ae): rename legacy MPAM build option

ENABLE_MPAM_FOR_LOWER_ELS was renamed to ENABLE_FEAT_MPAM a while ago,
but the rd1ae platform Makefile still carries the old name, probably due
to the ups

fix(rd1ae): rename legacy MPAM build option

ENABLE_MPAM_FOR_LOWER_ELS was renamed to ENABLE_FEAT_MPAM a while ago,
but the rd1ae platform Makefile still carries the old name, probably due
to the upstreaming overlapping with the rename.

Replace the old build option with the proper name, to make sure that
MPAM support gets compiled in without runtime checks.

Change-Id: If082e7250a7a3d12c7cbef5126303da1ee07a3af
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(versal2): enable system reset" into integration

Merge "feat(psci): remove cpu context init by index" into integration

chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEA

chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEATURE_DETECTION. So performing these checks in common code is
not the right place for this. Remove them and rely on FEATURE_DETECTION.

Change-Id: If3c25dcd7bc880f1f085bc6bb5270d8d1c4caf43
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

Introduce the is_feat_bti_{supported, present}() helpers and replace
checks for ENABLE_BTI with it. Also factor out the setting of
SCTLR_EL3.BT o

feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

Introduce the is_feat_bti_{supported, present}() helpers and replace
checks for ENABLE_BTI with it. Also factor out the setting of
SCTLR_EL3.BT out of the PAuth enablement and place it in the respective
entrypoints where we initialise SCTLR_EL3. This makes PAuth
self-contained and SCTLR_EL3 initialisation centralised.

Change-Id: I0c0657ff1e78a9652cd2cf1603478283dc01f17b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(guid-partition): fix MBR header load" into integration

Merge "docs(build): update GCC toolchain requirement to 14.2.Rel1" into integration

Merge "build(tlkd): add build error when building with FEAT_D128" into integration

fix(tsp): use %u to display unsigned values

When enabling -Wformat-signedness option, several warnings occur when
compiling TSP.
For example:
bl32/tsp/tsp_main.c: In function 'tsp_main':
include/com

fix(tsp): use %u to display unsigned values

When enabling -Wformat-signedness option, several warnings occur when
compiling TSP.
For example:
bl32/tsp/tsp_main.c: In function 'tsp_main':
include/common/debug.h:47:41: error: format '%d' expects argument of
type 'int', but argument 3 has type 'uint32_t' {aka 'unsigned int'}
[-Werror=format=]
47 | #define LOG_MARKER_INFO "\x28" /* 40 */
| ^~~~~~
include/common/debug.h:83:32: note: in expansion of macro
'LOG_MARKER_INFO'
83 | # define INFO(...) tf_log(LOG_MARKER_INFO __VA_ARGS__)
| ^~~~~~~~~~~~~~~
bl32/tsp/tsp_main.c:48:9: note: in expansion of macro 'INFO'
48 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on
requests\n",
| ^~~~

Use %u instead of %d to correct that (or PRIu64 instead of PRId64).

Change-Id: I50b4626d2090350c647bc9fd11a4d1bc174a4ee0
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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docs(changelog): put full name for Granule Protection Tables

As GPT can also stand for GUID Partition Tables (guid-partition topic),
put the full name for Granule Protection Tables title (gpt topic)

docs(changelog): put full name for Granule Protection Tables

As GPT can also stand for GUID Partition Tables (guid-partition topic),
put the full name for Granule Protection Tables title (gpt topic) to
avoid confusion.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6db8ee3c61f9af96d0919d975ca931beece6925d

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Merge changes from topic "xlnx_misra_fixes_versal" into integration

* changes:
fix(xilinx): resolve misra rule 8.3 violations
fix(xilinx): resolve misra rule 14.4 violation
fix(xilinx): resolv

Merge changes from topic "xlnx_misra_fixes_versal" into integration

* changes:
fix(xilinx): resolve misra rule 8.3 violations
fix(xilinx): resolve misra rule 14.4 violation
fix(xilinx): resolve misra rule 10.4 violations
fix(xilinx): resolve misra rule 10.3 violations

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fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c750561890

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c75056189075b1ba260e32426421e1e79a2e7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-I

refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-Id: I3c091eb8ff111c7bc030b32ad5948cbfaea3b35c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(mmc): fix the length of the response type

All MMC_RSP_* macros use BIT macro, which generates uint64_t types,
while the 'resp_type' member in 'struct mmc_cmd' is of type unsigned
int. Therefore,

fix(mmc): fix the length of the response type

All MMC_RSP_* macros use BIT macro, which generates uint64_t types,
while the 'resp_type' member in 'struct mmc_cmd' is of type unsigned
int. Therefore, the BIT_32 macro should be used instead.
Additionally, the JEDEC restricts the length of the Request/Response
Type to two bytes (16 bits).

Change-Id: I1d50f830786bcf9b9ed5c343217175cdeb03b243
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(mmc): fix the length of the ocr defines

All OCR_* macros use the BIT and GENMASK macros, which generate uint64_t
types. However, the 'ocr_voltage' member in 'struct mmc_device_info' is
of type u

fix(mmc): fix the length of the ocr defines

All OCR_* macros use the BIT and GENMASK macros, which generate uint64_t
types. However, the 'ocr_voltage' member in 'struct mmc_device_info' is
of type unsigned int. Therefore, the BIT_32 and GENMASK_32 macros should
be used instead. Additionally, JEDEC specifies that the length of the
OCR register is 32 bits.

Change-Id: I56eb1e60c7d514038b647bce498d0c10929d6b8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(guid-partition): fix MBR header load

In the case of GPT, the UEFI specification requires that the PMBR
(Protective MBR) partition table contain one partition record, which
starts at LBA 1, conta

fix(guid-partition): fix MBR header load

In the case of GPT, the UEFI specification requires that the PMBR
(Protective MBR) partition table contain one partition record, which
starts at LBA 1, containing the GPT Header. Hence, the field 'first_lba'
of the first partition table entry of the PMBR should always be set to 1
when GPT is used. However, this is not the case for plain MBR.

The function load_mbr_header() should also work for plain MBR
partitioning, so the check 'if (tmp.first_lba != 1)' has been relocated.

Change-Id: Iad990e61b2186c21f942537dfd140ed0e023ac4c
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(spm-mm): prevent excessive racing" into integration

Merge "perf(libc): use builtin implementations where possible" into integration

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of in

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
way of knowing the feature set of the waking core. If the two
diverge, the architectural feature discovery via ID registers breaks
down. We've thus far "fixed" this on a case by case basis which
doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
core has to initialise the context for when the core wakes up, but
should the core not powerdown it needs its old context intact. The only
way to work around this is by keeping two copies of context which
incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
it to make initialisation decisions. We can infer some of this from
registers that have already been written but this is awkwardly
limiting for what we can do. This also necessitates the split from
the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e

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fix(xilinx): resolve misra rule 8.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or function
with e

fix(xilinx): resolve misra rule 8.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or function
with external linkage is defined.
- Fix:
- Declared variable as static.

Change-Id: I44a022de3d5a62d255e2481dc1f4d1e8df2c7eb0
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 8.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.3:
- All declarations of an object or function shall use the same names
and type

fix(xilinx): resolve misra rule 8.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.3:
- All declarations of an object or function shall use the same names
and type qualifiers.
- Fix:
- Made same name parameters and type qualifiers in function declaration
and definition.

Change-Id: Idb4f986cec957102bb4ba1ef22f2e7937aaeb54d
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 14.4 violation

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.14.4:
- The controlling expression of an if statement and the controlling
expressi

fix(xilinx): resolve misra rule 14.4 violation

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.14.4:
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.
- Fix:
- Converted controlling expression of if statement into essential
Boolean type.

Change-Id: I2642ff4d6446bc0719d27cd95b1ad35c36f40211
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
ar

fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
- Fix:
- Made data type same for both the operands.

Change-Id: I0cea19477f3c10265d95ea1d5d2ea151dbf174bb
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 10.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narr

fix(xilinx): resolve misra rule 10.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category.
- Fix:
- Explicitly type casted to narrower essential type or of a different
essential type category.

Change-Id: Ia4258d2d0655f7847f832804a13d182ac0a2a29b
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neove

Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neoverse_rd): deprecate and remove RD-V1 platform variants
feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants
feat(neoverse_rd): deprecate and remove SGI-575 platform

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