Introduce ARM SiP service to switch execution state

In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether t

Introduce ARM SiP service to switch execution state

In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.

This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:

- raised from non-secure world;

- raised on the primary CPU, before any secondaries are brought online
with CPU_ON PSCI call;

- raised from an exception level immediately below EL3: EL2, if
implemented; otherwise NS EL1.

If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.

For the ARM SiP service:

- Add SMC function IDs for both AArch32 and AArch64;
- Increment the SiP service minor version to 2;
- Adjust the number of supported SiP service calls.

Add documentation for ARM SiP service.

Fixes ARM-software/tf-issues#436

Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Build: Correct Unix specific echo commands

Some recent changes have added direct use of the echo command without
parameters. This fails on a Windows shell, because echo without
parameters reports t

Build: Correct Unix specific echo commands

Some recent changes have added direct use of the echo command without
parameters. This fails on a Windows shell, because echo without
parameters reports the mode ("ECHO is on").
This is corrected using the ECHO_BLANK_LINE macro already provided
for that purpose.

Change-Id: I5fd7192861b4496f6f46b4f096e80a752cd135d6
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

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Build: Fix parallel build

2 problems were found, but are in one change to avoid submitting a patch
that might fail to build. The problems were:
1. The macro MAKE_PREREQ_DIR has a minor bug, in that

Build: Fix parallel build

2 problems were found, but are in one change to avoid submitting a patch
that might fail to build. The problems were:
1. The macro MAKE_PREREQ_DIR has a minor bug, in that it is capable of
generating recursive dependencies.
2. The inclusion of BUILD_DIR in TEMP_OBJ_DIRS left no explicit
dependency, BUILD_DIR might not exist when subdirectories are
created by a thread on another CPU.

This fix corrects these with the following changes:
1. MAKE_PREREQ_DIR does nothing for a direct self dependency.
2. BUILD_DIR is built using MAKE_PREREQ_DIR.
3. BUILD_DIR is an explicit prerequisite of all OBJ_DIRS.

Change-Id: I938cddea4a006df225c02a47b9cf759212f27fb7

Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

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Merge pull request #919 from davidcunado-arm/dc/smc_yielding_generic

Update terminology: standard SMC to yielding SMC

Add macro to check whether the CPU implements an EL

Replace all instances of checks with the new macro.

Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu

Add macro to check whether the CPU implements an EL

Replace all instances of checks with the new macro.

Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Fix execute-never permissions in xlat tables libs

Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setti

Fix execute-never permissions in xlat tables libs

Translation regimes that only support one virtual address space (such as
the ones for EL2 and EL3) can flag memory regions as execute-never by
setting to 1 the XN bit in the Upper Attributes field in the translation
tables descriptors. Translation regimes that support two different
virtual address spaces (such as the one shared by EL1 and EL0) use bits
PXN and UXN instead.

The Trusted Firmware runs at EL3 and EL1, it has to handle translation
tables of both translation regimes, but the previous code handled both
regimes the same way, as if both had only 1 VA range.

When trying to set a descriptor as execute-never it would set the XN
bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is
at the same bit position as UXN, which means that EL0 was being
prevented from executing code at this region, not EL1 as the code
intended. Therefore, the PXN bit was unset to 0 all the time. The result
is that, in AArch64 mode, read-only data sections of BL2 weren't
protected from being executed.

This patch adds support of translation regimes with two virtual address
spaces to both versions of the translation tables library, fixing the
execute-never permissions for translation tables in EL1.

The library currently does not support initializing translation tables
for EL0 software, therefore it does not set/unset the UXN bit. If EL1
software needs to initialize translation tables for EL0 software, it
should use a different library instead.

Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #923 from nmenon/fix_xlat_1

xlat lib: Don't set mmap_attr_t enum to be -1

xlat lib: Don't set mmap_attr_t enum to be -1

-1 is not a defined mmap_attr_t type. Instead of using invalid enum
types, we can either choose to define a INVALID type OR handle the
condition specifi

xlat lib: Don't set mmap_attr_t enum to be -1

-1 is not a defined mmap_attr_t type. Instead of using invalid enum
types, we can either choose to define a INVALID type OR handle the
condition specifically.

Since the usage of mmap_region_attr is limited, it is easier to just
handle the error condition specifically and return 0 or -1 depending
on success or fail.

Fixes: ARM-Software/tf-issues#473
Fixes: 28fa2e9ee8f4 ("xlat lib: Use mmap_attr_t type consistently")

Signed-off-by: Nishanth Menon <nm@ti.com>

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Merge pull request #896 from sbranden/tf_issue_461

Move defines in utils.h to utils_def.h to fix shared header compile i…

Merge pull request #913 from vwadekar/tegra-fixes-from-downstream

Tegra fixes from downstream

Tegra210: implement 'get_target_pwr_state' handler

This patch implements the handler to calculate the cluster and
system power states for the Tegra210 SoC. The power states
returned by this handler

Tegra210: implement 'get_target_pwr_state' handler

This patch implements the handler to calculate the cluster and
system power states for the Tegra210 SoC. The power states
returned by this handler are used by the PSCI library to decide
cache maintenance operations - cluster v cpu.

Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fix the NS DRAM address calculation logic

This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requireme

Tegra: fix the NS DRAM address calculation logic

This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.

Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: zero out NS Video memory carveout region

The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
B

Tegra: memctrl_v2: zero out NS Video memory carveout region

The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.

This patch adds the logic to zero out the previous memory carveout
region.

Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: calculate proper power state for cluster/system power down

Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a c

Tegra186: calculate proper power state for cluster/system power down

Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a cluster power down.

This patch fixes this anomaly and sets the correct power state during a
cluster/system power down.

Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: max retries for ARI requests

This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signe

Tegra186: mce: max retries for ARI requests

This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memmap Tegra micro-seconds timer controller

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a8719

Tegra: memmap Tegra micro-seconds timer controller

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: early init the delay timer

This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.

Change-Id

Tegra: early init the delay timer

This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.

Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge branch 'integration' into tf_issue_461

Move defines in utils.h to utils_def.h to fix shared header compile issues

utils.h is included in various header files for the defines in it.
Some of the other header files only contain defines. Th

Move defines in utils.h to utils_def.h to fix shared header compile issues

utils.h is included in various header files for the defines in it.
Some of the other header files only contain defines. This allows the
header files to be shared between host and target builds for shared defines.

Recently types.h has been included in utils.h as well as some function
prototypes.

Because of the inclusion of types.h conflicts exist building host tools
abd these header files now. To solve this problem,
move the defines to utils_def.h and have this included by utils.h and
change header files to only include utils_def.h and not pick up the new
types.h being introduced.

Fixes ARM-software/tf-issues#461

Signed-off-by: Scott Branden <scott.branden@broadcom.com>

Remove utils_def.h from utils.h

This patch removes utils_def.h from utils.h as it is not required.
And also makes a minor change to ensure Juno platform compiles.

Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29

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Merge pull request #920 from vwadekar/asserts-release-nvidia

Asserts release nvidia

Tegra: Control inclusion of helper code used for asserts

One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such co

Tegra: Control inclusion of helper code used for asserts

One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such code
so that it is based on the ENABLE_ASSERTIONS build option.

Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: enable asserts by default

This patch enables the assert in the context save routine
by default, for all flavours of the build.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: enable 'ENABLE_ASSERTIONS' for all builds

This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to
1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in
C asser

Tegra: enable 'ENABLE_ASSERTIONS' for all builds

This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to
1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in
C assertions in release mode.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: group platform settings together

This patch groups all the platform configuration macros into
the common platform.mk makefile.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>