Merge pull request #964 from soby-mathew/sm/rsapss_sup

Add support for RSASSAPSS algorithm

Merge pull request #963 from soby-mathew/sm/scmi_dev

Add SCMI power domain and system power protocol support

Merge pull request #961 from jeenu-arm/gic-600

Introduce ARM GIC-600 driver

Merge pull request #960 from jeenu-arm/cpu-libs

Add support for Cortex-A75 and Cortex-A55 CPUs

Merge pull request #962 from antonio-nino-diaz-arm/an/fwu-checks

FWU: Check for overlaps when loading images, introduce `FWU_SMC_IMAGE_RESET`

Add SCMI support for Juno platform

This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_ma

Add SCMI support for Juno platform

This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_map` array.

Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

CSS: Add SCMI driver for SCP

This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented

CSS: Add SCMI driver for SCP

This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented in the driver. The SCP power management
abstraction layer for SCMI for CSS power management is also added.

A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI
driver over SCPI.

[1] ARM System Control and Management Interface v1.0 (SCMI)
Document number: ARM DEN 0056A

Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

cert_create: Use RSASSA-PSS signature scheme for certificates

This patch modifies the `cert_create` tool to use RSASSA-PSS scheme for
signing the certificates. This is compliant with RSA PKCS_2_1 st

cert_create: Use RSASSA-PSS signature scheme for certificates

This patch modifies the `cert_create` tool to use RSASSA-PSS scheme for
signing the certificates. This is compliant with RSA PKCS_2_1 standard as
mandated by TBBR.

Note that the certificates generated by using cert_create tool after this
patch can be authenticated during TBB only if the corresponding mbedtls
driver in ARM Trusted Firmware has the corresponding support.

Change-Id: If224f41c76b3c4765ae2af5259e67f73602818a4
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

Add support for RSASSAPSS algorithm in mbedtls crypto driver

This patch adds support for RSASSA-PSS Signature Algorithm for
X509 certificates in mbedtls crypto driver. Now the driver supports
RSA PK

Add support for RSASSAPSS algorithm in mbedtls crypto driver

This patch adds support for RSASSA-PSS Signature Algorithm for
X509 certificates in mbedtls crypto driver. Now the driver supports
RSA PKCS2_1 standard as mandated by TBBR.

NOTE: With this patch, the PKCS1_5 standard compliant RSA signature
is deprecated.

Change-Id: I9cf6d073370b710cc36a7b374a55ec96c0496461
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

Increase heapsize for mbedtls library

The mbedTLS library requires larger heap memory for verification of RSASSA-PSS
signature in certificates during Trusted Board Boot. This patch increases the
hea

Increase heapsize for mbedtls library

The mbedTLS library requires larger heap memory for verification of RSASSA-PSS
signature in certificates during Trusted Board Boot. This patch increases the
heap memory for the same.

Change-Id: I3c3123d7142b7b7b01463516ec436734895da159
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

Update the path for firmware_image_package.h in firmware-design.md

Change-Id: Ic0a9b3c6d212e7171b37f944e11f079282dcce87
Signed-off-by: Summer Qin <summer.qin@arm.com>

Device tree changes to boot FreeBSD on FVPs

FreeBSD does not understand #interrupt-map in a device tree. This prevents the
GIC from being set up correctly. This patch removes the #interrupt-map in t

Device tree changes to boot FreeBSD on FVPs

FreeBSD does not understand #interrupt-map in a device tree. This prevents the
GIC from being set up correctly. This patch removes the #interrupt-map in the
device trees for the Base and Foundation FVPs. This enables correct boot of
FreeBSD on these platforms.

These changes have been tested with FreeBSD and an Ubuntu cloud image
(ubuntu-16.04-server-cloudimg-arm64-uefi1.img) to ensure compatibility with
Linux.

Change-Id: I1347acdcf994ec4b1dd843ba32af9951aa54db73
Signed-off-by: Achin Gupta <achin.gupta@arm.com>

show more ...

FWU: Introduce FWU_SMC_IMAGE_RESET

This SMC is as a means for the image loading state machine to go from
COPYING, COPIED or AUTHENTICATED states to RESET state. Previously, this
was only done when t

FWU: Introduce FWU_SMC_IMAGE_RESET

This SMC is as a means for the image loading state machine to go from
COPYING, COPIED or AUTHENTICATED states to RESET state. Previously, this
was only done when the authentication of an image failed or when the
execution of the image finished.

Documentation updated.

Change-Id: Ida6d4c65017f83ae5e27465ec36f54499c6534d9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

FWU: Check for overlaps when loading images

Added checks to FWU_SMC_IMAGE_COPY to prevent loading data into a
memory region where another image data is already loaded.

Without this check, if two im

FWU: Check for overlaps when loading images

Added checks to FWU_SMC_IMAGE_COPY to prevent loading data into a
memory region where another image data is already loaded.

Without this check, if two images are configured to be loaded in
overlapping memory regions, one of them can be loaded and
authenticated and the copy function is still able to load data from
the second image on top of the first one. Since the first image is
still in authenticated state, it can be executed, which could lead to
the execution of unauthenticated arbitrary code of the second image.

Firmware update documentation updated.

Change-Id: Ib6871e569794c8e610a5ea59fe162ff5dcec526c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Remove `DISABLE_PEDANTIC` build option

It doesn't make sense to use the `-pedantic` flag when building the
Trusted Firmware as we use GNU extensions and so our code is not
fully ISO C compliant. Thi

Remove `DISABLE_PEDANTIC` build option

It doesn't make sense to use the `-pedantic` flag when building the
Trusted Firmware as we use GNU extensions and so our code is not
fully ISO C compliant. This flag only makes sense if the code intends to
be ISO C compliant.

Change-Id: I6273564112759ff57f03b273f5349733a5f38aef
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Introduce ARM GIC-600 driver

ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed t

Introduce ARM GIC-600 driver

ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.

The driver provides APIs for Redistributor power management, and
overrides those in the generic GICv3 driver. The driver data is shared
between generic GICv3 driver and that of GIC-600.

For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER
is set to FVP_GIC600. Also update user guide.

Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

Add support for Cortex-A75 and Cortex-A55 CPUs

Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardwa

Add support for Cortex-A75 and Cortex-A55 CPUs

Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.

Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

Merge pull request #957 from hzhuang1/finish_hikey_psci

Finish hikey psci

Merge pull request #958 from antonio-nino-diaz-arm/an/mbedtls-heap-size

mbedtls: Define optimized mbed TLS heap size

mbedtls: Define optimized mbed TLS heap size

mbed TLS provides the debug API `mbedtls_memory_buffer_alloc_status()`
to analyse the RAM usage of the library.

When RSA is selected as algorithm, the m

mbedtls: Define optimized mbed TLS heap size

mbed TLS provides the debug API `mbedtls_memory_buffer_alloc_status()`
to analyse the RAM usage of the library.

When RSA is selected as algorithm, the maximum heap usage in FVP and
Juno has been determined empirically to be approximately 5.5 KiB.
However, The default heap size used when RSA is selected is 8 KiB.

This patch reduces the buffer from 8 KiB to 6 KiB so that the BSS
sections of both BL1 and BL2 are 2 KiB smaller when the firmware is
compiled with TBB support.

Change-Id: I43878a4e7af50c97be9c8d027c728c8483f24fbf
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Merge pull request #955 from hzhuang1/ufs

Add ufs stack and designware phy

Merge pull request #956 from hzhuang1/fix_var_in_ddr

hikey: fix uninitialized variable in ddr code

hikey: pm: finish PSCI hook functions

This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
S

hikey: pm: finish PSCI hook functions

This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

show more ...

hikey: bl31: enable CCI port for cluster 0

The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.

Signed-off-by: Leo Yan <leo.yan@linaro.org>

hikey: bl31: enable CCI port for cluster 0

The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

show more ...

hikey: fix for CPU topology

Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.

Signed-off-by: Leo Yan <leo.yan@l

hikey: fix for CPU topology

Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

show more ...