1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 ARM_MAP_TSP_SEC_MEM, 83 #if TRUSTED_BOARD_BOOT 84 /* To access the Root of Trust Public Key registers. */ 85 MAP_DEVICE2, 86 #endif 87 #if ARM_BL31_IN_DRAM 88 ARM_MAP_BL31_SEC_DRAM, 89 #endif 90 #ifdef SPD_opteed 91 ARM_OPTEE_PAGEABLE_LOAD_MEM, 92 #endif 93 {0} 94 }; 95 #endif 96 #ifdef IMAGE_BL2U 97 const mmap_region_t plat_arm_mmap[] = { 98 MAP_DEVICE0, 99 V2M_MAP_IOFPGA, 100 {0} 101 }; 102 #endif 103 #ifdef IMAGE_BL31 104 const mmap_region_t plat_arm_mmap[] = { 105 ARM_MAP_SHARED_RAM, 106 V2M_MAP_IOFPGA, 107 MAP_DEVICE0, 108 MAP_DEVICE1, 109 {0} 110 }; 111 #endif 112 #ifdef IMAGE_BL32 113 const mmap_region_t plat_arm_mmap[] = { 114 #ifdef AARCH32 115 ARM_MAP_SHARED_RAM, 116 #endif 117 V2M_MAP_IOFPGA, 118 MAP_DEVICE0, 119 MAP_DEVICE1, 120 {0} 121 }; 122 #endif 123 124 ARM_CASSERT_MMAP 125 126 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 127 static const int fvp_cci400_map[] = { 128 PLAT_FVP_CCI400_CLUS0_SL_PORT, 129 PLAT_FVP_CCI400_CLUS1_SL_PORT, 130 }; 131 132 static const int fvp_cci5xx_map[] = { 133 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 134 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 135 }; 136 137 static unsigned int get_interconnect_master(void) 138 { 139 unsigned int master; 140 u_register_t mpidr; 141 142 mpidr = read_mpidr_el1(); 143 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 144 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 145 146 assert(master < FVP_CLUSTER_COUNT); 147 return master; 148 } 149 #endif 150 151 /******************************************************************************* 152 * A single boot loader stack is expected to work on both the Foundation FVP 153 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 154 * SYS_ID register provides a mechanism for detecting the differences between 155 * these platforms. This information is stored in a per-BL array to allow the 156 * code to take the correct path.Per BL platform configuration. 157 ******************************************************************************/ 158 void fvp_config_setup(void) 159 { 160 unsigned int rev, hbi, bld, arch, sys_id; 161 162 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 163 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 164 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 165 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 166 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 167 168 if (arch != ARCH_MODEL) { 169 ERROR("This firmware is for FVP models\n"); 170 panic(); 171 } 172 173 /* 174 * The build field in the SYS_ID tells which variant of the GIC 175 * memory is implemented by the model. 176 */ 177 switch (bld) { 178 case BLD_GIC_VE_MMAP: 179 ERROR("Legacy Versatile Express memory map for GIC peripheral" 180 " is not supported\n"); 181 panic(); 182 break; 183 case BLD_GIC_A53A57_MMAP: 184 break; 185 default: 186 ERROR("Unsupported board build %x\n", bld); 187 panic(); 188 } 189 190 /* 191 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 192 * for the Foundation FVP. 193 */ 194 switch (hbi) { 195 case HBI_FOUNDATION_FVP: 196 arm_config.flags = 0; 197 198 /* 199 * Check for supported revisions of Foundation FVP 200 * Allow future revisions to run but emit warning diagnostic 201 */ 202 switch (rev) { 203 case REV_FOUNDATION_FVP_V2_0: 204 case REV_FOUNDATION_FVP_V2_1: 205 case REV_FOUNDATION_FVP_v9_1: 206 case REV_FOUNDATION_FVP_v9_6: 207 break; 208 default: 209 WARN("Unrecognized Foundation FVP revision %x\n", rev); 210 break; 211 } 212 break; 213 case HBI_BASE_FVP: 214 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 215 216 /* 217 * Check for supported revisions 218 * Allow future revisions to run but emit warning diagnostic 219 */ 220 switch (rev) { 221 case REV_BASE_FVP_V0: 222 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 223 break; 224 case REV_BASE_FVP_REVC: 225 arm_config.flags |= (ARM_CONFIG_FVP_SHIFTED_AFF | 226 ARM_CONFIG_FVP_HAS_SMMUV3 | 227 ARM_CONFIG_FVP_HAS_CCI5XX); 228 break; 229 default: 230 WARN("Unrecognized Base FVP revision %x\n", rev); 231 break; 232 } 233 break; 234 default: 235 ERROR("Unsupported board HBI number 0x%x\n", hbi); 236 panic(); 237 } 238 } 239 240 241 void fvp_interconnect_init(void) 242 { 243 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 244 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 245 ERROR("Unrecognized CCN variant detected. Only CCN-502" 246 " is supported"); 247 panic(); 248 } 249 250 plat_arm_interconnect_init(); 251 #else 252 uintptr_t cci_base = 0; 253 const int *cci_map = 0; 254 unsigned int map_size = 0; 255 256 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 257 ARM_CONFIG_FVP_HAS_CCI5XX))) { 258 return; 259 } 260 261 /* Initialize the right interconnect */ 262 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 263 cci_base = PLAT_FVP_CCI5XX_BASE; 264 cci_map = fvp_cci5xx_map; 265 map_size = ARRAY_SIZE(fvp_cci5xx_map); 266 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 267 cci_base = PLAT_FVP_CCI400_BASE; 268 cci_map = fvp_cci400_map; 269 map_size = ARRAY_SIZE(fvp_cci400_map); 270 } 271 272 assert(cci_base); 273 assert(cci_map); 274 cci_init(cci_base, cci_map, map_size); 275 #endif 276 } 277 278 void fvp_interconnect_enable(void) 279 { 280 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 281 plat_arm_interconnect_enter_coherency(); 282 #else 283 unsigned int master; 284 285 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 286 ARM_CONFIG_FVP_HAS_CCI5XX)) { 287 master = get_interconnect_master(); 288 cci_enable_snoop_dvm_reqs(master); 289 } 290 #endif 291 } 292 293 void fvp_interconnect_disable(void) 294 { 295 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 296 plat_arm_interconnect_exit_coherency(); 297 #else 298 unsigned int master; 299 300 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 301 ARM_CONFIG_FVP_HAS_CCI5XX)) { 302 master = get_interconnect_master(); 303 cci_disable_snoop_dvm_reqs(master); 304 } 305 #endif 306 } 307