1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <platform_def.h> 12 #include <tbbr_img_def.h> 13 #include <utils_def.h> 14 #include <xlat_tables_defs.h> 15 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define ARM_SYSTEM_COUNT 1 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in ARM platforms encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define ARM_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define ARM_LOCAL_STATE_RET 1 44 /* Local power state for OFF/power-down. Valid for CPU and cluster power 45 domains */ 46 #define ARM_LOCAL_STATE_OFF 2 47 48 /* Memory location options for TSP */ 49 #define ARM_TRUSTED_SRAM_ID 0 50 #define ARM_TRUSTED_DRAM_ID 1 51 #define ARM_DRAM_ID 2 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define ARM_TRUSTED_SRAM_BASE 0x04000000 55 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 56 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 57 58 /* The remaining Trusted SRAM is used to load the BL images */ 59 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 60 ARM_SHARED_RAM_SIZE) 61 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 62 ARM_SHARED_RAM_SIZE) 63 64 /* 65 * The top 16MB of DRAM1 is configured as secure access only using the TZC 66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 68 */ 69 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 70 71 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 72 ARM_DRAM1_SIZE - \ 73 ARM_SCP_TZC_DRAM1_SIZE) 74 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 75 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 76 ARM_SCP_TZC_DRAM1_SIZE - 1) 77 78 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 79 ARM_DRAM1_SIZE - \ 80 ARM_TZC_DRAM1_SIZE) 81 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 82 ARM_SCP_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 84 ARM_AP_TZC_DRAM1_SIZE - 1) 85 86 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 87 #if ARM_CRYPTOCELL_INTEG 88 /* 89 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 90 * This is required by CryptoCell to authenticate BL33 which is loaded 91 * into the Non Secure DDR. 92 */ 93 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 94 #else 95 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 96 #endif 97 98 #ifdef SPD_opteed 99 /* 100 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 101 * load/authenticate the trusted os extra image. The first 512KB of 102 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 103 * for OPTEE is paged image which only include the paging part using 104 * virtual memory but without "init" data. OPTEE will copy the "init" data 105 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 106 * extra image behind the "init" data. 107 */ 108 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 109 ARM_AP_TZC_DRAM1_SIZE - \ 110 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 111 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 112 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 113 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 114 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 115 MT_MEMORY | MT_RW | MT_SECURE) 116 #endif /* SPD_opteed */ 117 118 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 119 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 120 ARM_TZC_DRAM1_SIZE) 121 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 122 ARM_NS_DRAM1_SIZE - 1) 123 124 #define ARM_DRAM1_BASE ULL(0x80000000) 125 #define ARM_DRAM1_SIZE ULL(0x80000000) 126 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 127 ARM_DRAM1_SIZE - 1) 128 129 #define ARM_DRAM2_BASE ULL(0x880000000) 130 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 131 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 132 ARM_DRAM2_SIZE - 1) 133 134 #define ARM_IRQ_SEC_PHY_TIMER 29 135 136 #define ARM_IRQ_SEC_SGI_0 8 137 #define ARM_IRQ_SEC_SGI_1 9 138 #define ARM_IRQ_SEC_SGI_2 10 139 #define ARM_IRQ_SEC_SGI_3 11 140 #define ARM_IRQ_SEC_SGI_4 12 141 #define ARM_IRQ_SEC_SGI_5 13 142 #define ARM_IRQ_SEC_SGI_6 14 143 #define ARM_IRQ_SEC_SGI_7 15 144 145 /* 146 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 147 * terminology. On a GICv2 system or mode, the lists will be merged and treated 148 * as Group 0 interrupts. 149 */ 150 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 151 ARM_IRQ_SEC_SGI_1, \ 152 ARM_IRQ_SEC_SGI_2, \ 153 ARM_IRQ_SEC_SGI_3, \ 154 ARM_IRQ_SEC_SGI_4, \ 155 ARM_IRQ_SEC_SGI_5, \ 156 ARM_IRQ_SEC_SGI_7 157 158 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 159 ARM_IRQ_SEC_SGI_6 160 161 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 162 ARM_SHARED_RAM_BASE, \ 163 ARM_SHARED_RAM_SIZE, \ 164 MT_DEVICE | MT_RW | MT_SECURE) 165 166 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 167 ARM_NS_DRAM1_BASE, \ 168 ARM_NS_DRAM1_SIZE, \ 169 MT_MEMORY | MT_RW | MT_NS) 170 171 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 172 TSP_SEC_MEM_BASE, \ 173 TSP_SEC_MEM_SIZE, \ 174 MT_MEMORY | MT_RW | MT_SECURE) 175 176 #if ARM_BL31_IN_DRAM 177 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 178 BL31_BASE, \ 179 PLAT_ARM_MAX_BL31_SIZE, \ 180 MT_MEMORY | MT_RW | MT_SECURE) 181 #endif 182 183 /* 184 * The number of regions like RO(code), coherent and data required by 185 * different BL stages which need to be mapped in the MMU. 186 */ 187 #if USE_COHERENT_MEM 188 #define ARM_BL_REGIONS 3 189 #else 190 #define ARM_BL_REGIONS 2 191 #endif 192 193 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 194 ARM_BL_REGIONS) 195 196 /* Memory mapped Generic timer interfaces */ 197 #define ARM_SYS_CNTCTL_BASE 0x2a430000 198 #define ARM_SYS_CNTREAD_BASE 0x2a800000 199 #define ARM_SYS_TIMCTL_BASE 0x2a810000 200 201 #define ARM_CONSOLE_BAUDRATE 115200 202 203 /* Trusted Watchdog constants */ 204 #define ARM_SP805_TWDG_BASE 0x2a490000 205 #define ARM_SP805_TWDG_CLK_HZ 32768 206 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 207 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 208 #define ARM_TWDG_TIMEOUT_SEC 128 209 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 210 ARM_TWDG_TIMEOUT_SEC) 211 212 /****************************************************************************** 213 * Required platform porting definitions common to all ARM standard platforms 214 *****************************************************************************/ 215 216 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 217 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 218 219 /* 220 * This macro defines the deepest retention state possible. A higher state 221 * id will represent an invalid or a power down state. 222 */ 223 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 224 225 /* 226 * This macro defines the deepest power down states possible. Any state ID 227 * higher than this is invalid. 228 */ 229 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 230 231 /* 232 * Some data must be aligned on the biggest cache line size in the platform. 233 * This is known only to the platform as it might have a combination of 234 * integrated and external caches. 235 */ 236 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 237 238 239 /******************************************************************************* 240 * BL1 specific defines. 241 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 242 * addresses. 243 ******************************************************************************/ 244 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 245 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 246 + PLAT_ARM_TRUSTED_ROM_SIZE) 247 /* 248 * Put BL1 RW at the top of the Trusted SRAM. 249 */ 250 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 251 ARM_BL_RAM_SIZE - \ 252 PLAT_ARM_MAX_BL1_RW_SIZE) 253 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 254 255 /******************************************************************************* 256 * BL2 specific defines. 257 ******************************************************************************/ 258 #if ARM_BL31_IN_DRAM || defined(AARCH32) 259 /* 260 * For AArch32 BL31 is not applicable. 261 * For AArch64 BL31 is loaded in the DRAM. 262 * Put BL2 just below BL1. 263 */ 264 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 265 #define BL2_LIMIT BL1_RW_BASE 266 #else 267 /* 268 * Put BL2 just below BL31. 269 */ 270 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 271 #define BL2_LIMIT BL31_BASE 272 #endif 273 274 /******************************************************************************* 275 * BL31 specific defines. 276 ******************************************************************************/ 277 #if ARM_BL31_IN_DRAM 278 /* 279 * Put BL31 at the bottom of TZC secured DRAM 280 */ 281 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 282 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 283 PLAT_ARM_MAX_BL31_SIZE) 284 #else 285 /* 286 * Put BL31 at the top of the Trusted SRAM. 287 */ 288 #define BL31_BASE (ARM_BL_RAM_BASE + \ 289 ARM_BL_RAM_SIZE - \ 290 PLAT_ARM_MAX_BL31_SIZE) 291 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 292 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 293 #endif 294 295 /******************************************************************************* 296 * BL32 specific defines. 297 ******************************************************************************/ 298 /* 299 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 300 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 301 * controller. 302 */ 303 #if ARM_BL31_IN_DRAM 304 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 305 PLAT_ARM_MAX_BL31_SIZE) 306 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 307 PLAT_ARM_MAX_BL31_SIZE) 308 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 309 PLAT_ARM_MAX_BL31_SIZE) 310 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 311 ARM_AP_TZC_DRAM1_SIZE) 312 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 313 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 314 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 315 # define TSP_PROGBITS_LIMIT BL2_BASE 316 # define BL32_BASE ARM_BL_RAM_BASE 317 # define BL32_LIMIT BL31_BASE 318 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 319 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 320 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 321 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 322 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 323 + (1 << 21)) 324 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 325 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 326 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 327 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 328 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 329 ARM_AP_TZC_DRAM1_SIZE) 330 #else 331 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 332 #endif 333 334 /* BL32 is mandatory in AArch32 */ 335 #ifndef AARCH32 336 #ifdef SPD_none 337 #undef BL32_BASE 338 #endif /* SPD_none */ 339 #endif 340 341 /******************************************************************************* 342 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 343 ******************************************************************************/ 344 #define BL2U_BASE BL2_BASE 345 #if ARM_BL31_IN_DRAM || defined(AARCH32) 346 /* 347 * For AArch32 BL31 is not applicable. 348 * For AArch64 BL31 is loaded in the DRAM. 349 * BL2U extends up to BL1. 350 */ 351 #define BL2U_LIMIT BL1_RW_BASE 352 #else 353 /* BL2U extends up to BL31. */ 354 #define BL2U_LIMIT BL31_BASE 355 #endif 356 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 357 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 358 359 /* 360 * ID of the secure physical generic timer interrupt used by the TSP. 361 */ 362 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 363 364 365 /* 366 * One cache line needed for bakery locks on ARM platforms 367 */ 368 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 369 370 371 #endif /* __ARM_DEF_H__ */ 372