Merge pull request #1361 from vchong/tool_add_img

poplar: rename FIP_ADD_IMG to TOOL_ADD_IMG

Remove the unused macro NDEBUG

The C standards specify that this macro is used to
disable asserts but, in our code, the assert macro
is controlled with ENABLE_ASSERTIONS. Having this macro
here crea

Remove the unused macro NDEBUG

The C standards specify that this macro is used to
disable asserts but, in our code, the assert macro
is controlled with ENABLE_ASSERTIONS. Having this macro
here creates confusion about the behaviour of assert.

Change-Id: Iab8689a14dc2b8790729857d56585ce43c0c4f51
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1363 from antonio-nino-diaz-arm/an/res1-ap

xlat: Set AP[1] to 1 when it is RES1

Merge pull request #1360 from antonio-nino-diaz-arm/an/smccc-v2

Add support for the SMC Calling Convention 2.0

ARM platforms: Demonstrate mem_protect from el3_runtime

Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstra

ARM platforms: Demonstrate mem_protect from el3_runtime

Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates
mem_protect from el3_runtime firmware on ARM Platforms specifically
when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent
in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap
tables temporarily and then the protected regions are then cleared. This
avoids the need to map the non secure DRAM permanently to BL31/sp_min.

The stack size is also increased, because DYNAMIC_XLAT_TABLES require
a bigger stack.

Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1255 from masahir0y/int-ll64

Use consistent int-ll64 typedefs for aarch32 and aarch64

cert_create: fix makefile to remove executable on 'make realclean'

Spurious whitespace existed in the BINARY shell variable which meant
the cert_tool executable was not being removed on 'make realcl

cert_create: fix makefile to remove executable on 'make realclean'

Spurious whitespace existed in the BINARY shell variable which meant
the cert_tool executable was not being removed on 'make realclean'.

Change-Id: Ibfd2fd17889514f6613e33c6df58d53b9232ec14
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>

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checkpatch: Ignore SPDX_LICENSE_TAG

The Linux kernel expects the SPDX license tag in the first line of each
source code file in a comment.

In the context of the Linux kernel repository this makes s

checkpatch: Ignore SPDX_LICENSE_TAG

The Linux kernel expects the SPDX license tag in the first line of each
source code file in a comment.

In the context of the Linux kernel repository this makes sense because
they have many different license headers across their codebase. Moving
the tag to the first line of the source code files makes it easier for
analyzers to see the license of each file.

In the Trusted Firmware, we control all headers and make sure that they
follow the same pattern, so this is not needed.

Change-Id: Ie19802c7b65b1bdd63da9ece64311aec1f8ad7fe
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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types: use int-ll64 for both aarch32 and aarch64

Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch

types: use int-ll64 for both aarch32 and aarch64

Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch32 and aarch64.

For example, uint64_t is defined as 'unsigned long long' for aarch32
and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined
as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64.

A problem typically arises when you use printf() in common code.

One solution could be, to cast the arguments to a type long enough
for both architectures. For example, if 'val' is uint64_t type,
like this:

printf("val = %llx\n", (unsigned long long)val);

Or, somebody may suggest to use a macro provided by <inttypes.h>,
like this:

printf("val = %" PRIx64 "\n", val);

But, both would make the code ugly.

The solution adopted in Linux kernel is to use the same typedefs for
all architectures. The fixed integer types in the kernel-space have
been unified into int-ll64, like follows:

typedef signed char int8_t;
typedef unsigned char uint8_t;

typedef signed short int16_t;
typedef unsigned short uint16_t;

typedef signed int int32_t;
typedef unsigned int uint32_t;

typedef signed long long int64_t;
typedef unsigned long long uint64_t;

[ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ]

This gets along with the codebase shared between 32 bit and 64 bit,
with the data model called ILP32, LP64, respectively.

The width for primitive types is defined as follows:

ILP32 LP64
int 32 32
long 32 64
long long 64 64
pointer 32 64

'long long' is 64 bit for both, so it is used for defining uint64_t.
'long' has the same width as pointer, so for uintptr_t.

We still need an ifdef conditional for (s)size_t.

All 64 bit architectures use "unsigned long" size_t, and most 32 bit
architectures use "unsigned int" size_t. H8/300, S/390 are known as
exceptions; they use "unsigned long" size_t despite their architecture
is 32 bit.

One idea for simplification might be to define size_t as 'unsigned long'
across architectures, then forbid the use of "%z" string format.
However, this would cause a distortion between size_t and sizeof()
operator. We have unknowledge about the native type of sizeof(), so
we need a guess of it anyway. I want the following formula to always
return 1:

__builtin_types_compatible_p(size_t, typeof(sizeof(int)))

Fortunately, ARM is probably a majority case. As far as I know, all
32 bit ARM compilers use "unsigned int" size_t.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arch_helpers: use u_register_t for register read/write

u_register_t is preferred rather than uint64_t. This is more
consistent with the aarch32 implementation.

Signed-off-by: Masahiro Yamada <yama

arch_helpers: use u_register_t for register read/write

u_register_t is preferred rather than uint64_t. This is more
consistent with the aarch32 implementation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Fix pointer type mismatch of handlers

Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side. Fix the typ

Fix pointer type mismatch of handlers

Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side. Fix the type mismatch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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BL2_AT_EL3: do not try to disable MMU twice on AARCH32

If BL2_AT_EL3 is enabled, bl2_run_next_image is called at the end of BL2.
This function calls disable_mmu_icache_secure.
It is then useless to

BL2_AT_EL3: do not try to disable MMU twice on AARCH32

If BL2_AT_EL3 is enabled, bl2_run_next_image is called at the end of BL2.
This function calls disable_mmu_icache_secure.
It is then useless to call it in bl2_main in that case.

fixes arm-software/tf-issues#582

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge pull request #1345 from dbasehore/udelay

rockchip/rk3399: Fix sram_udelay

xlat: Set AP[1] to 1 when it is RES1

According to the ARMv8 ARM issue C.a:

AP[1] is valid only for stage 1 of a translation regime that can
support two VA ranges. It is RES 1 when stage 1 t

xlat: Set AP[1] to 1 when it is RES1

According to the ARMv8 ARM issue C.a:

AP[1] is valid only for stage 1 of a translation regime that can
support two VA ranges. It is RES 1 when stage 1 translations can
support only one VA range.

This means that, even though this bit is ignored, it should be set to 1
in the EL3 and EL2 translation regimes.

For translation regimes consisting on EL0 and a higher regime this bit
selects between control at EL0 or at the higher Exception level. The
regimes that support two VA ranges are EL1&0 and EL2&0 (the later one
is only available since ARMv8.1).

This fix has to be applied to both versions of the translation tables
library.

Change-Id: If19aaf588551bac7aeb6e9a686cf0c2068e7c181
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Remove dtc warnings

DTC generates warnings when unit names begin with 0, or
when a node containing a reg or range property doesn't have a unit name
in the node name. This patch fixes those cases.

C

Remove dtc warnings

DTC generates warnings when unit names begin with 0, or
when a node containing a reg or range property doesn't have a unit name
in the node name. This patch fixes those cases.

Change-Id: If24ec68ef3034fb3fcefb96c5625c47a0bbd8474
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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poplar: rename FIP_ADD_IMG to TOOL_ADD_IMG

Fixes: f3d522b ("poplar: Support Trusted OS extra image (OP-TEE header) parsing")
Signed-off-by: Victor Chong <victor.chong@linaro.org>

Add support for the SMC Calling Convention 2.0

Due to differences in the bitfields of the SMC IDs, it is not possible
to support SMCCC 1.X and 2.0 at the same time.

The behaviour of `SMCCC_MAJOR_VE

Add support for the SMC Calling Convention 2.0

Due to differences in the bitfields of the SMC IDs, it is not possible
to support SMCCC 1.X and 2.0 at the same time.

The behaviour of `SMCCC_MAJOR_VERSION` has changed. Now, it is a build
option that specifies the major version of the SMCCC that the Trusted
Firmware supports. The only two allowed values are 1 and 2, and it
defaults to 1. The value of `SMCCC_MINOR_VERSION` is derived from it.

Note: Support for SMCCC v2.0 is an experimental feature to enable
prototyping of secure partition specifications. Support for this
convention is disabled by default and could be removed without notice.

Change-Id: I88abf9ccf08e9c66a13ce55c890edea54d9f16a7
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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spd: add static qualifier to locally used functions and data

These are used locally in a file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Merge pull request #1358 from omasab/sgi575_mt_flag

css/sgi575: enable ARM_PLAT_MT flag

Merge pull request #1357 from antonio-nino-diaz-arm/an/fix-misra

Fix some MISRA defects in SPM code

css/sgi575: enable ARM_PLAT_MT flag

SGI-575 platform is based on Cortex-A75 processor which has its MT bit
in the MPIDR register set to '1'. So the Arm platform layer code has
to be made aware of th

css/sgi575: enable ARM_PLAT_MT flag

SGI-575 platform is based on Cortex-A75 processor which has its MT bit
in the MPIDR register set to '1'. So the Arm platform layer code has
to be made aware of this.

Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>

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Fix some MISRA defects in SPM code

Change-Id: I989c1f4aef8e3cb20d5d19e6347575e6449bb60b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1250 from jollysxilinx/zynqmp-new-eemi-api

plat/xilinx: Add support for new platform management APIs for ZynqMP

Merge pull request #1346 from samarthp/sp/support-multiple-mhu-gen

plat/arm: Add MHUv2 support to SCMI driver

plat/arm: Add MHUv2 support to SCMI driver

Currently the SCMI driver supports MHUv1, but Arm platforms may have
varied versions of MHU driver, with MHUv2 controllers being in the
latest Arm platform

plat/arm: Add MHUv2 support to SCMI driver

Currently the SCMI driver supports MHUv1, but Arm platforms may have
varied versions of MHU driver, with MHUv2 controllers being in the
latest Arm platforms.

This patch updates the SCMI driver to support MHUv2, specifically that
the sender must send the wake-up to the receiver before initiating any
data transfer.

Also, the existing mhu driver files, css_mhu.c and css_mhu.h, have been
moved from the scpi directory to a new directory, css/drivers/mhu.

Change-Id: I9b46b492a3e1d9e26db12d83a9773958a8c8402f
Signed-off-by: Samarth Parikh <samarth.parikh@arm.com>

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