1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; 20 21 /* 22 * Returns 1 if the provided granule size is supported, 0 otherwise. 23 */ 24 int xlat_arch_is_granule_size_supported(size_t size) 25 { 26 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 27 28 if (size == (4U * 1024U)) { 29 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 30 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 31 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 32 } else if (size == (16U * 1024U)) { 33 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 34 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 35 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 36 } else if (size == (64U * 1024U)) { 37 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 38 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 39 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 40 } 41 42 return 0; 43 } 44 45 size_t xlat_arch_get_max_supported_granule_size(void) 46 { 47 if (xlat_arch_is_granule_size_supported(64U * 1024U)) { 48 return 64U * 1024U; 49 } else if (xlat_arch_is_granule_size_supported(16U * 1024U)) { 50 return 16U * 1024U; 51 } else { 52 assert(xlat_arch_is_granule_size_supported(4U * 1024U)); 53 return 4U * 1024U; 54 } 55 } 56 57 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 58 { 59 /* Physical address can't exceed 48 bits */ 60 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 61 62 /* 48 bits address */ 63 if (max_addr & ADDR_MASK_44_TO_47) 64 return TCR_PS_BITS_256TB; 65 66 /* 44 bits address */ 67 if (max_addr & ADDR_MASK_42_TO_43) 68 return TCR_PS_BITS_16TB; 69 70 /* 42 bits address */ 71 if (max_addr & ADDR_MASK_40_TO_41) 72 return TCR_PS_BITS_4TB; 73 74 /* 40 bits address */ 75 if (max_addr & ADDR_MASK_36_TO_39) 76 return TCR_PS_BITS_1TB; 77 78 /* 36 bits address */ 79 if (max_addr & ADDR_MASK_32_TO_35) 80 return TCR_PS_BITS_64GB; 81 82 return TCR_PS_BITS_4GB; 83 } 84 85 #if ENABLE_ASSERTIONS 86 /* 87 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 88 * supported in ARMv8.2 onwards. 89 */ 90 static const unsigned int pa_range_bits_arr[] = { 91 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 92 PARANGE_0101, PARANGE_0110 93 }; 94 95 unsigned long long xlat_arch_get_max_supported_pa(void) 96 { 97 u_register_t pa_range = read_id_aa64mmfr0_el1() & 98 ID_AA64MMFR0_EL1_PARANGE_MASK; 99 100 /* All other values are reserved */ 101 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 102 103 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 104 } 105 #endif /* ENABLE_ASSERTIONS*/ 106 107 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 108 { 109 if (ctx->xlat_regime == EL1_EL0_REGIME) { 110 assert(xlat_arch_current_el() >= 1); 111 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 112 } else { 113 assert(ctx->xlat_regime == EL3_REGIME); 114 assert(xlat_arch_current_el() >= 3); 115 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 116 } 117 } 118 119 120 void xlat_arch_tlbi_va(uintptr_t va) 121 { 122 #if IMAGE_EL == 1 123 assert(IS_IN_EL(1)); 124 xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); 125 #elif IMAGE_EL == 3 126 assert(IS_IN_EL(3)); 127 xlat_arch_tlbi_va_regime(va, EL3_REGIME); 128 #endif 129 } 130 131 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime) 132 { 133 /* 134 * Ensure the translation table write has drained into memory before 135 * invalidating the TLB entry. 136 */ 137 dsbishst(); 138 139 /* 140 * This function only supports invalidation of TLB entries for the EL3 141 * and EL1&0 translation regimes. 142 * 143 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 144 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 145 */ 146 if (xlat_regime == EL1_EL0_REGIME) { 147 assert(xlat_arch_current_el() >= 1); 148 tlbivaae1is(TLBI_ADDR(va)); 149 } else { 150 assert(xlat_regime == EL3_REGIME); 151 assert(xlat_arch_current_el() >= 3); 152 tlbivae3is(TLBI_ADDR(va)); 153 } 154 } 155 156 void xlat_arch_tlbi_va_sync(void) 157 { 158 /* 159 * A TLB maintenance instruction can complete at any time after 160 * it is issued, but is only guaranteed to be complete after the 161 * execution of DSB by the PE that executed the TLB maintenance 162 * instruction. After the TLB invalidate instruction is 163 * complete, no new memory accesses using the invalidated TLB 164 * entries will be observed by any observer of the system 165 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 166 * "Ordering and completion of TLB maintenance instructions". 167 */ 168 dsbish(); 169 170 /* 171 * The effects of a completed TLB maintenance instruction are 172 * only guaranteed to be visible on the PE that executed the 173 * instruction after the execution of an ISB instruction by the 174 * PE that executed the TLB maintenance instruction. 175 */ 176 isb(); 177 } 178 179 int xlat_arch_current_el(void) 180 { 181 int el = GET_EL(read_CurrentEl()); 182 183 assert(el > 0); 184 185 return el; 186 } 187 188 void setup_mmu_cfg(unsigned int flags, 189 const uint64_t *base_table, 190 unsigned long long max_pa, 191 uintptr_t max_va) 192 { 193 uint64_t mair, ttbr, tcr; 194 uintptr_t virtual_addr_space_size; 195 196 /* Set attributes in the right indices of the MAIR. */ 197 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 198 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 199 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 200 201 ttbr = (uint64_t) base_table; 202 203 /* 204 * Limit the input address ranges and memory region sizes translated 205 * using TTBR0 to the given virtual address space size. 206 */ 207 assert(max_va < ((uint64_t) UINTPTR_MAX)); 208 209 virtual_addr_space_size = max_va + 1; 210 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 211 212 /* 213 * __builtin_ctzll(0) is undefined but here we are guaranteed that 214 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 215 */ 216 tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); 217 218 /* 219 * Set the cacheability and shareability attributes for memory 220 * associated with translation table walks. 221 */ 222 if ((flags & XLAT_TABLE_NC) != 0) { 223 /* Inner & outer non-cacheable non-shareable. */ 224 tcr |= TCR_SH_NON_SHAREABLE | 225 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 226 } else { 227 /* Inner & outer WBWA & shareable. */ 228 tcr |= TCR_SH_INNER_SHAREABLE | 229 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 230 } 231 232 /* 233 * It is safer to restrict the max physical address accessible by the 234 * hardware as much as possible. 235 */ 236 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 237 238 #if IMAGE_EL == 1 239 assert(IS_IN_EL(1)); 240 /* 241 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 242 * translated using TTBR1_EL1. 243 */ 244 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 245 #elif IMAGE_EL == 3 246 assert(IS_IN_EL(3)); 247 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 248 #endif 249 250 mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair; 251 mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr; 252 253 /* Set TTBR bits as well */ 254 if (ARM_ARCH_AT_LEAST(8, 2)) { 255 /* 256 * Enable CnP bit so as to share page tables with all PEs. This 257 * is mandatory for ARMv8.2 implementations. 258 */ 259 ttbr |= TTBR_CNP_BIT; 260 } 261 262 mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr; 263 mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32); 264 } 265