History log of /rk3399_ARM-atf/ (Results 1476 – 1500 of 18586)
Revision Date Author Comments
(<<< Hide modified files)
(Show modified files >>>)
9cc1539003-Jul-2025 Joanna Farley <joanna.farley@arm.com>

Merge changes from topic "xlnx_fix_plat_ns_entry" into integration

* changes:
feat(versal2): validate non-secure entry addr
feat(versal2): parse reserve memory subnodes

f1f04d7805-Feb-2021 Jiafei Pan <Jiafei.Pan@nxp.com>

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A0

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A009663 was not applied due to missing define.

Change-Id: I4f3669adf02dea487f89f81d2fc7344bb65f830d
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

show more ...

e8c3fddb24-Apr-2025 Prasad Kummari <prasad.kummari@amd.com>

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:

The value of an object with automatic storage duration shall
not be read before it has been set.Initializ

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:

The value of an object with automatic storage duration shall
not be read before it has been set.Initialized the variable
to default value zero.

Change-Id: Ib3a2a853b82ce3c3ba1f518705d7ac2e01130e37
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

f3d9e22a22-Apr-2025 Prasad Kummari <prasad.kummari@amd.com>

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:

The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:

The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.

Change-Id: Ibd402a52e44e59d1c37613d8925aac8e115aa31c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

e0c4d39001-Jul-2025 Yann Gautier <yann.gautier@st.com>

Merge changes from topic "xlnx_fix_gen_con_datatype" into integration

* changes:
fix(console): typecast operands to match data type
fix(console): typecast operands to match data type

27e7222125-Jun-2025 Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and ch

feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and checks if entry point lies within a valid
non-secure region.

Change-Id: Iff998fe855f5de8fbd96f0d7d4b0d7c33c904d34
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

59eaed0325-Jun-2025 Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point

feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point address during a hot plug event

Change-Id: I8cdb098509bd3b06f0df5ea647220bdbb8a4bf35
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

36b998d727-Jun-2025 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "fix(lx2160): set snoop-delayed exclusive handling on A72 cores" into integration

b8d63a7a22-Mar-2025 Kai Liang <kai.liang@mediatek.corp-partner.google.com>

feat(mt8189): add hotplug driver

Minor hardware changes require minor driver updates.

Signed-off-by: Kai Liang <kai.liang@mediatek.com>
Change-Id: Iaeed93a7cf1b8c22979fedf7bd571f30398d410e

c97b2c8026-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "feat(lib): add mmio read with timeout" into integration

6cd0ff2c26-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(mt8196): duplicated ETIMEDOUT definition" into integration

f927412726-Jun-2025 Bipin Ravi <bipin.ravi@arm.com>

Merge "fix(cpus): workaround for Cortex-A710 erratum 1927200" into integration

9bfd8ffb26-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "feat(mt8189): add dfd driver" into integration

b1bca91e26-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "feat(ti): enable power state validation for K3 SoCs" into integration

1ee5db3c26-Jun-2025 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(psci): do not modify higher levels for standby in OSI mode" into integration

01d24d6906-Jun-2025 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

feat(nxp-mmc): add timeout to blocking loops

Replace all register polling loops with timeout-enabled versions,
allowing the caller to decide whether to panic or handle the error
gracefully.

Change-

feat(nxp-mmc): add timeout to blocking loops

Replace all register polling loops with timeout-enabled versions,
allowing the caller to decide whether to panic or handle the error
gracefully.

Change-Id: If296f06a20cb849e690d1193bda1378508d3f7e0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

7a1970f421-May-2025 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it a

feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it allows the system to log an error and
delegate the decision to the caller - whether to continue execution
or halt with a panic.

To address this, the mmio_read_poll_timeout() helper can be used. It
exits with -ETIMEDOUT if the timeout is reached, or 0 on success.
Additionally, the final value read from the register is stored in the
'val' variable, avoiding the need for an extra read after polling
completes.

Change-Id: I2ef53299b12ece6bc7be0e1234d5c2708e36ecf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

0e039eaf17-Jun-2025 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

fix(mt8196): duplicated ETIMEDOUT definition

Refactor the local definition of the ETIMEDOUT macro to prevent
conflicts with the standard definition provided by libc/errno.h.

Change-Id: I3eff7e4a8e3

fix(mt8196): duplicated ETIMEDOUT definition

Refactor the local definition of the ETIMEDOUT macro to prevent
conflicts with the standard definition provided by libc/errno.h.

Change-Id: I3eff7e4a8e395914cb6a4b33d18e6d5b46cc06f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

b34be5df10-Apr-2025 Boyan Karatotev <boyan.karatotev@arm.com>

fix(psci): do not modify higher levels for standby in OSI mode

The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not

fix(psci): do not modify higher levels for standby in OSI mode

The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not bother
saving level 0. It will also clamp the level it accesses to the
end_pwrlvl argument. Well, in the fast path, this argument is always 0
(as a condition of entering the fast path). The result is that it reads
the level 0 power state (retention) and writes it to the level 1 power
state, even though by definition, the fast path will not update higher
power levels.

The fix is to pass PLAT_MAX_PWR_LVL instead of target_pwrlvl to
psci_update_req_local_pwr_states(). However, doing that makes it
apparent that this call will not change anything and therefore there is
nothing to save - the level 0 power state is written by
psci_set_cpu_local_state(). So the save + restore are redundant. Remove
them to save on a bunch of work.

Another thing that is not considered is locking. No locks are held in
the fast path, so these updates are not safe.

Change-Id: Icc785df87b294b938b59705116369abd80ccf4da
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

4040019721-May-2025 Alexander Stein <alexander.stein@ew.tq-group.com>

fix(layerscape): unlock write access SMMU_CBn_ACTLR

This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure

fix(layerscape): unlock write access SMMU_CBn_ACTLR

This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure states. This mimics the changes from commit 0ca1d8fba
("fix(layerscape): unlock write access SMMU_CBn_ACTLR")

[1] https://developer.arm.com/documentation/epm133458/latest

Change-Id: I3f1e35150f66c604be2e10b3f91b39b2a7dc62bd
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

show more ...

5e192ddf25-Jun-2025 Joanna Farley <joanna.farley@arm.com>

Merge "fix(xilinx): add API to get powerdown request status" into integration

aed177ce24-Jun-2025 Runyang Chen <runyang.chen@mediatek.com>

feat(mt8189): add dfd driver

Add dfd init flow.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: Iaad7a46d019a7bf5ae86ca7583291975e01bfbfb

d90bb65023-Jun-2025 Manish Pandey <manish.pandey2@arm.com>

Merge "build(handoff)!: switch to LibTL submodule" into integration

9e7679ed23-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "feat(tc): add support for configuring DSU settings" into integration

0f39b7e623-Jun-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(nxp-crypto): restricts generating nxp_mkvb via ns-world" into integration

1...<<51525354555657585960>>...744