1 /*
2 * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <arch_helpers.h>
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9 #include <dfd.h>
10 #include <plat_dfd.h>
11
12 struct dfd_mcu_ext_pair {
13 uint32_t reg;
14 uint32_t val;
15 };
16
17 static const struct dfd_mcu_ext_pair ext_init_array[] = {
18 { DFD_INTERNAL_CTL, 0x0018200D },
19 { DFD_INTERNAL_PWR_ON, 0x0000000B },
20 { DFD_INTERNAL_SHIFT_CLK_RATIO, 0x00000000 },
21 { DFD_INTERNAL_TEST_SO_OVER_64, 0x00000001 },
22 { DFD_TEST_SI_0, 0x00000000 },
23 { DFD_TEST_SI_1, 0x00000000 },
24 { DFD_TEST_SI_2, 0x00000000 },
25 { DFD_TEST_SI_3, 0x00000000 },
26 { DFD_INTERNAL_CHAIN_GROUP, 0x00000013 },
27 { DFD_INTERNAL_CHAIN_INV_INFO_LL, 0x00000002 },
28 { DFD_INTERNAL_CHAIN_INV_INFO_LH, 0x40444444 },
29 { DFD_INTERNAL_CHAIN_INV_INFO_HL, 0x00000040 },
30 { DFD_INTERNAL_CHAIN_INV_INFO_HH, 0x00000000 },
31 { DFD_POWER_CTL, 0x000000F9 },
32 { DFD_READ_ADDR, 0x000000F9 },
33 { DFD_V50_GROUP_0_1_DIFF, 1 },
34 { DFD_V50_GROUP_0_2_DIFF, 236 },
35 { DFD_V50_GROUP_0_3_DIFF, 1466 },
36 { DFD_V50_GROUP_0_4_DIFF, 4885 },
37 { DFD_V50_GROUP_0_5_DIFF, 17935 },
38 { DFD_V50_GROUP_0_6_DIFF, 22364 },
39 { DFD_V50_GROUP_0_7_DIFF, 23268 },
40 { DFD_V50_GROUP_0_8_DIFF, 31878 },
41 { DFD_V50_GROUP_0_9_DIFF, 31879 },
42 { DFD_V50_GROUP_0_10_DIFF, 35472 },
43 { DFD_V50_GROUP_0_11_DIFF, 35473 },
44 { DFD_V50_GROUP_0_12_DIFF, 35540 },
45 { DFD_V50_GROUP_0_13_DIFF, 36145 },
46 { DFD_V50_GROUP_0_14_DIFF, 37666 },
47 { DFD_V50_GROUP_0_15_DIFF, 37667 },
48 { DFD_V50_GROUP_0_16_DIFF, 46039 },
49 { DFD_V50_GROUP_0_17_DIFF, 48314 },
50 { DFD_V50_GROUP_0_18_DIFF, 48705 },
51 { DFD_V50_GROUP_0_19_DIFF, 0 },
52 { DFD_V50_GROUP_0_20_DIFF, 0 },
53 { DFD_V50_GROUP_0_21_DIFF, 0 },
54 { DFD_V50_GROUP_0_22_DIFF, 0 },
55 { DFD_V50_GROUP_0_23_DIFF, 0 },
56 { DFD_V50_GROUP_0_24_DIFF, 0 },
57 { DFD_V50_GROUP_0_25_DIFF, 0 },
58 { DFD_V50_GROUP_0_26_DIFF, 0 },
59 { DFD_V50_GROUP_0_27_DIFF, 0 },
60 { DFD_V50_GROUP_0_28_DIFF, 0 },
61 { DFD_V50_GROUP_0_29_DIFF, 0 },
62 { DFD_V50_GROUP_0_30_DIFF, 0 },
63 { DFD_V50_GROUP_0_31_DIFF, 0 },
64 { DFD_V50_GROUP_0_32_DIFF, 0 },
65 { DFD_V50_GROUP_0_33_DIFF, 0 },
66 { DFD_V50_GROUP_0_34_DIFF, 0 },
67 { DFD_V50_GROUP_0_35_DIFF, 0 },
68 { DFD_V50_GROUP_0_36_DIFF, 0 },
69 { DFD_V50_GROUP_0_37_DIFF, 0 },
70 { DFD_V50_GROUP_0_38_DIFF, 0 },
71 { DFD_V50_GROUP_0_39_DIFF, 0 },
72 { DFD_V50_GROUP_0_40_DIFF, 0 },
73 { DFD_V50_GROUP_0_41_DIFF, 0 },
74 { DFD_V50_GROUP_0_42_DIFF, 0 },
75 { DFD_V50_GROUP_0_43_DIFF, 0 },
76 { DFD_V50_GROUP_0_44_DIFF, 0 },
77 { DFD_V50_GROUP_0_45_DIFF, 0 },
78 { DFD_V50_GROUP_0_46_DIFF, 0 },
79 { DFD_V50_GROUP_0_47_DIFF, 0 },
80 { DFD_V50_GROUP_0_48_DIFF, 0 },
81 { DFD_V50_GROUP_0_49_DIFF, 0 },
82 { DFD_V50_GROUP_0_50_DIFF, 0 },
83 { DFD_V50_GROUP_0_51_DIFF, 0 },
84 { DFD_V50_GROUP_0_52_DIFF, 0 },
85 { DFD_V50_GROUP_0_53_DIFF, 0 },
86 { DFD_V50_GROUP_0_54_DIFF, 0 },
87 { DFD_V50_GROUP_0_55_DIFF, 0 },
88 { DFD_V50_GROUP_0_56_DIFF, 0 },
89 { DFD_V50_GROUP_0_57_DIFF, 0 },
90 { DFD_V50_GROUP_0_58_DIFF, 0 },
91 { DFD_V50_GROUP_0_59_DIFF, 0 },
92 { DFD_V50_GROUP_0_60_DIFF, 0 },
93 { DFD_V50_GROUP_0_61_DIFF, 0 },
94 { DFD_V50_GROUP_0_62_DIFF, 0 },
95 { DFD_V50_GROUP_0_63_DIFF, 0x00000001 },
96 { DFD_V50_CHAIN_GROUP_3_0_INFO, 0x00100400 },
97 { DFD_V50_CHAIN_GROUP_7_4_INFO, 0x0b0a0a0a },
98 { DFD_V50_CHAIN_GROUP_11_8_INFO, 0x12120b0b },
99 { DFD_V50_CHAIN_GROUP_15_12_INFO, 0x08080812 },
100 { DFD_V50_CHAIN_GROUP_19_16_INFO, 0x09090909 },
101 { DFD_V50_CHAIN_GROUP_23_20_INFO, 0x0e0e0d05 },
102 { DFD_V50_CHAIN_GROUP_27_24_INFO, 0x0e0e0e0e },
103 { DFD_V50_CHAIN_GROUP_31_28_INFO, 0x0e0e0e0e },
104 { DFD_V50_CHAIN_GROUP_35_32_INFO, 0x06070f0f },
105 { DFD_V50_CHAIN_GROUP_39_36_INFO, 0x06070c06 },
106 { DFD_V50_CHAIN_GROUP_43_40_INFO, 0x06070c06 },
107 { DFD_V50_CHAIN_GROUP_47_44_INFO, 0x06070c06 },
108 { DFD_V50_CHAIN_GROUP_51_48_INFO, 0x06070c06 },
109 { DFD_V50_CHAIN_GROUP_55_52_INFO, 0x06070c06 },
110 { DFD_V50_CHAIN_GROUP_59_56_INFO, 0x00000c06 },
111 { DFD_V50_CHAIN_GROUP_63_60_INFO, 0x11030000 },
112 { DFD_V50_CHAIN_GROUP_67_64_INFO, 0x00000002 },
113 { DFD_V50_CHAIN_GROUP_71_68_INFO, 0x11030101 },
114 { DFD_V50_CHAIN_GROUP_75_72_INFO, 0x00000002 },
115 { DFD_V50_CHAIN_GROUP_79_76_INFO, 0x00000101 },
116 { DFD_V50_CHAIN_GROUP_83_80_INFO, 0x00000000 },
117 { DFD_V50_CHAIN_GROUP_87_84_INFO, 0x00000000 },
118 { DFD_V50_CHAIN_GROUP_91_88_INFO, 0x00000000 },
119 { DFD_V50_CHAIN_GROUP_95_92_INFO, 0x00000000 },
120 { DFD_V50_CHAIN_GROUP_99_96_INFO, 0x00000000 },
121 { DFD_V50_CHAIN_GROUP_103_100_INFO, 0x00000000 },
122 { DFD_V50_CHAIN_GROUP_107_104_INFO, 0x00000000 },
123 { DFD_V50_CHAIN_GROUP_111_108_INFO, 0x00000000 },
124 { DFD_V50_CHAIN_GROUP_115_112_INFO, 0x00000000 },
125 { DFD_V50_CHAIN_GROUP_119_116_INFO, 0x00000000 },
126 { DFD_V50_CHAIN_GROUP_123_120_INFO, 0x00000000 },
127 { DFD_V50_CHAIN_GROUP_127_124_INFO, 0x00000000 },
128 };
129
130 static uint64_t dfd_cache_dump;
131 static bool dfd_enabled;
132 static uint64_t dfd_base_addr;
133 static uint64_t dfd_chain_length;
134
dfd_setup(uint64_t base_addr,uint64_t chain_length,uint64_t cache_dump)135 void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump)
136 {
137 unsigned int i;
138
139 mmio_write_32(DFD_INTERNAL_CHAIN_LENGTH_0, chain_length);
140 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
141
142 /* setup global variables for suspend and resume */
143 dfd_enabled = true;
144 dfd_base_addr = base_addr;
145 dfd_chain_length = chain_length;
146 dfd_cache_dump = cache_dump;
147
148 for (i = 0; i < ARRAY_SIZE(ext_init_array); i++)
149 mmio_write_32(ext_init_array[i].reg, ext_init_array[i].val);
150
151 if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
152 sync_writel(DFD_V35_ENABLE, 0x1);
153 sync_writel(DFD_V35_TAP_NUMBER, 0xB);
154 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
155 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
156 }
157 dsbsy();
158 }
159
dfd_resume(void)160 void dfd_resume(void)
161 {
162 if (dfd_enabled == true) {
163 dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
164 }
165 }
166