zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is be

zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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drivers: imx: imx_gpt: Add general purpose timer API binding

Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.

[bod: changed name from imx_delay_ti

drivers: imx: imx_gpt: Add general purpose timer API binding

Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.

[bod: changed name from imx_delay_timer -> imx_gpt ]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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Fix broken links in documentation

Change-Id: Ic58f88fa4e5fc0004a33357915ff80db30954441
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Support shared Mbed TLS heap for SGM

Change-Id: Ibbfedb6601feff51dfb82c1d94850716c5a36d24
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Support shared Mbed TLS heap for SGI

Change-Id: Iac454c745543842bfeed004aee7a3f4fb94d37e1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Reduce BL2 size for FVP

This patch reduces BL2 size by 12kB. Thanks to the shared Mbed TLS heap
between BL1 and BL2, BL2 now requires less memory since it doesn't need
to allocate a heap anymore.

C

Reduce BL2 size for FVP

This patch reduces BL2 size by 12kB. Thanks to the shared Mbed TLS heap
between BL1 and BL2, BL2 now requires less memory since it doesn't need
to allocate a heap anymore.

Change-Id: I58a15f8c424273650c9f55112abe88105b6cdbae
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Support shared Mbed TLS heap for FVP

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not a

Support shared Mbed TLS heap for FVP

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Prepare Mbed TLS drivers for shared heap

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being acces

Prepare Mbed TLS drivers for shared heap

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge pull request #1548 from BayLibre/opteed

opteed: pass power level on suspend

Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09

Marvell updates 18.09

fix: tools: Fix doimage syntax breaking secure mode build

Missing ")" in fprintf causing build break in secure boot mode.

Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac
Signed-off-by: Konstan

fix: tools: Fix doimage syntax breaking secure mode build

Missing ")" in fprintf causing build break in secure boot mode.

Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: Update Marvell base code version to 18.09.1

Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: svc: ap807: add SVC configuration for AP807

- add svc configuration according to values burnt
to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine

plat: svc: ap807: add SVC configuration for AP807

- add svc configuration according to values burnt
to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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tools: doimage: Add secure image key file examples

Add example keys for building trusted flash images using
doimage tools.
Similar files can be generated using openssl or mbedtls.
Marvell platform m

tools: doimage: Add secure image key file examples

Add example keys for building trusted flash images using
doimage tools.
Similar files can be generated using openssl or mbedtls.
Marvell platform make files are using trusted boot
configurations from this example etst vector.

Change-Id: I38a2e295171bee4c14005ce6f020b352c683496e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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fix: marvell: Check the required libraries before building doimage

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for e

fix: marvell: Check the required libraries before building doimage

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.

Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

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plat: a8k: enable PMU overflow interrupt handler

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on d

plat: a8k: enable PMU overflow interrupt handler

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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marvell: drivers: correct RTC init sequence

It turned out that resetting the RTC time register is not
necessary during initial configuration. Safely remove it
from the sequence.

Change-Id: Id2b9c7d

marvell: drivers: correct RTC init sequence

It turned out that resetting the RTC time register is not
necessary during initial configuration. Safely remove it
from the sequence.

Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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gicv2: enable configuring IRQ trigger type

This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful t

gicv2: enable configuring IRQ trigger type

This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.

Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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Merge pull request #1484 from nathan-menhorn/tee-validate-header-603

Update optee_utils.c to fix ARM-software/tf-issues#603

Merge pull request #1541 from rajanv-xilinx/integration-num-clocks

zynqmp: pm: Add API to get number of clocks

Merge pull request #1551 from glneo/k3-pwr-down-psci

Add PSCI core power down for K3

marvell: pm: do not panic by default in cpu_standby

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent o

marvell: pm: do not panic by default in cpu_standby

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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mvebu: cp110: fix spelling in register definition

Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).

Change-Id:

mvebu: cp110: fix spelling in register definition

Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).

Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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mvebu: cp110: align all comphy_index arguments type

The biggest comphy index can be equal to 6 so there is no need to use
uint64_t for storing it.

Change-Id: I14c2b68e51678a560815963c72aed0c37068f9

mvebu: cp110: align all comphy_index arguments type

The biggest comphy index can be equal to 6 so there is no need to use
uint64_t for storing it.

Change-Id: I14c2b68e51678a560815963c72aed0c37068f926
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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plat: marvell: a80x0: reconfigure CP0 PCIE0 windows

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SAT

plat: marvell: a80x0: reconfigure CP0 PCIE0 windows

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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