S-EL2 Support: Check for AArch64

Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.

S-EL2 Support: Check for AArch64

Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7

show more ...

Add support for enabling S-EL2

This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
respons

Add support for enabling S-EL2

This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
responsibility to check if S-EL2 is available on the system before requesting
this EL through the entry point information.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1

show more ...

Merge changes from topic "bs/libc" into integration

* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AAr

Merge changes from topic "bs/libc" into integration

* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AArch32/64

show more ...

libc: Consolidate the size_t and NULL definitions

Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header

Signed-off-by: Bence Szépkúti <bence.szepkut

libc: Consolidate the size_t and NULL definitions

Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82

show more ...

libc: Consolidate unified definitions

As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems coun

libc: Consolidate unified definitions

As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems counterproductive

The int128 types were left un-unified as __int128 is not supported by
gcc on AArch32

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf

show more ...

libc: Unify intmax_t and uintmax_t on AArch32/64

Conceptually, these are supposed to be the largest integers
representable in C, but GCC and Clang define them as long long for
compatibility.

Signed

libc: Unify intmax_t and uintmax_t on AArch32/64

Conceptually, these are supposed to be the largest integers
representable in C, but GCC and Clang define them as long long for
compatibility.

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I7c0117f3be167342814d260a371889120dcf6576

show more ...

Merge changes from topic "allwinner_bl31_size" into integration

* changes:
Reduce space lost to object alignment
imx: Fix multiple definition of ipc_handle
imx: Fix missing inclusion of cdefs.h

Merge "intel: Refactor common platform code [5/5]" into integration

Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c

Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]

show more ...

Merge "Remove -Wunused-const-variable warning" into integration

Merge "rockchip: px30: Add support for UART3 as serial output" into integration

Merge "Enable Link Time Optimization in GCC" into integration

Reduce space lost to object alignment

Currently, sections within .text/.rodata/.data/.bss are emitted in the
order they are seen by the linker. This leads to wasted space, when a
section with a larg

Reduce space lost to object alignment

Currently, sections within .text/.rodata/.data/.bss are emitted in the
order they are seen by the linker. This leads to wasted space, when a
section with a larger alignment follows one with a smaller alignment.
We can avoid this wasted space by sorting the sections.

To take full advantage of this, we must disable generation of common
symbols, so "common" data can be sorted along with the rest of .bss.

An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`:
.text => no change
.rodata => 16 bytes saved
.data => 11 bytes saved
.bss => 576 bytes saved

As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it
easier to spot bugs in header files.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51

show more ...

imx: Fix multiple definition of ipc_handle

This is not conforming C and does not compile with -fno-common.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b

imx: Fix multiple definition of ipc_handle

This is not conforming C and does not compile with -fno-common.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b91e3f50975b073

show more ...

imx: Fix missing inclusion of cdefs.h

This was found by compiling with -fno-common:

./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/rele

imx: Fix missing inclusion of cdefs.h

This was found by compiling with -fno-common:

./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here

__packed was intended to be the attribute macro from cdefs.h, not an
object of the structure type.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a

show more ...

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
th

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6

show more ...

Remove -Wunused-const-variable warning

-Wunused-const-variable=1 is already included by -Wunused-variable,
which is part of -Wall. -Wunused-const-variable=2, which is what we have
been using as part

Remove -Wunused-const-variable warning

-Wunused-const-variable=1 is already included by -Wunused-variable,
which is part of -Wall. -Wunused-const-variable=2, which is what we have
been using as part of W=1, warns for unused static const variables in
headers, which will likely produce a lot of false positives that will
take a large effort to fix.

Additionally, some of these issues may be caused by different builds of
TF-A where some features are used in some builds and ignored in others.

Change-Id: Ifa0b16a75344cc1f6240e8d5745005f8f2046d34
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

show more ...

Merge "Enable -Wlogical-op always" into integration

Merge "Enable -Wshadow always" into integration

Merge "Remove unnecessary warning options" into integration

Merge "Refactor the warning flags" into integration

Merge "plat/rockchip: initialize reset and poweroff GPIOs with known invalid value" into integration

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: int

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: introduce plat_enable_console()
Tegra: include: drivers: introduce spe.h
Tegra194: update nvg header to v6.4
Tegra194: mce: enable strict checking
Tegra194: CC6 state from last offline CPU in the cluster
Tegra194: console driver compilation from platform makefiles
Tegra194: memctrl: platform handler for TZDRAM setup
Tegra194: memctrl: override SE client as coherent
Tegra194: save system suspend entry marker to TZDRAM
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
Tegra194: cleanup references to Tegra186
Tegra194: mce: display NVG header version during boot
Tegra194: mce: fix cg_cstate encoding format
Tegra194: drivers: SE and RNG1/PKA1 context save support
Tegra194: rename secure scratch register macros
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Tegra194: mce: remove unsupported functionality
Tegra194: sanity check target cluster during core power on
Tegra194: fix defects flagged by MISRA scan
Tegra194: mce: fix defects flagged by MISRA scan
Tegra194: remove the GPU reset register macro
Tegra194: MC registers to allow CPU accesses to TZRAM
Tegra194: increase MAX_MMAP_REGIONS macro value
Tegra194: update nvg header to v6.1
Tegra194: update cache operations supported by the ROC
Tegra194: memctrl: platform handlers to reprogram MSS
Tegra194: core and cluster count values
Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
Tegra194: add MC_SECURITY mask defines
Tegra194: Update wake mask, wake time for cpu offlining
Tegra194: program stream ids for XUSB
Tegra194: Update checks for c-state stats
Tegra194: smmu: fix mask for board revision id
Tegra194: smmu: ISO support
Tegra194: Initialize smmu on system suspend exit
Tegra194: Update cpu core-id calculation
Tegra194: read-modify-write ACTLR_ELx registers
Tegra194: Enable fake system suspend
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
Tegra194: platform support for memctrl/smmu drivers
Tegra194: Support for cpu suspend

show more ...

Enable Link Time Optimization in GCC

This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.

LTO is enabled only for aarch64

Enable Link Time Optimization in GCC

This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.

LTO is enabled only for aarch64 as there seem to be
a bug in the aarch32 compiler when LTO is enabled.

The changes in the makefiles include:
- Adding -flto and associated flags to enable LTO.
- Using gcc as a wrapper at link time instead of ld.
This is recommended when using LTO as gcc internally
takes care of invoking the necessary plugins for LTO.
- Adding switches to pass options to ld.
- Adding a flag to disable fix for erratum cortex-a53-843419
unless explicitly enabled. This is needed because GCC
seem to automatically add the erratum fix when used
as a wrapper for LD.

Additionally, this patch updates the TF-A user guide with
the new build option.

Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468

show more ...

Merge "Changes to support updated register usage in SMCCC v1.2" into integration