1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_mailbox.h" 14 #include "socfpga_sip_svc.h" 15 16 /* Number of SiP Calls implemented */ 17 #define SIP_NUM_CALLS 0x3 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block; 23 static int read_block; 24 static int current_buffer; 25 static int send_id; 26 static int rcv_id; 27 static int max_blocks; 28 static uint32_t bytes_per_block; 29 static uint32_t blocks_submitted; 30 31 struct fpga_config_info { 32 uint32_t addr; 33 int size; 34 int size_written; 35 uint32_t write_requested; 36 int subblocks_sent; 37 int block_number; 38 }; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else 72 args[2] = bytes_per_block; 73 74 buffer->size_written += args[2]; 75 mailbox_send_cmd_async( 76 send_id++ % MBOX_MAX_JOB_ID, 77 MBOX_RECONFIG_DATA, 78 args, 3, 0); 79 80 buffer->subblocks_sent++; 81 max_blocks--; 82 } 83 84 return !max_blocks; 85 } 86 87 static int intel_fpga_sdm_write_all(void) 88 { 89 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 90 if (intel_fpga_sdm_write_buffer( 91 &fpga_config_buffers[current_buffer])) 92 break; 93 return 0; 94 } 95 96 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 97 { 98 uint32_t ret; 99 100 if (query_type == 1) 101 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); 102 else 103 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); 104 105 if (ret) { 106 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 107 return INTEL_SIP_SMC_STATUS_BUSY; 108 else 109 return INTEL_SIP_SMC_STATUS_ERROR; 110 } 111 112 return INTEL_SIP_SMC_STATUS_OK; 113 } 114 115 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 116 { 117 int i; 118 119 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 120 if (fpga_config_buffers[i].block_number == current_block) { 121 fpga_config_buffers[i].subblocks_sent--; 122 if (fpga_config_buffers[i].subblocks_sent == 0 123 && fpga_config_buffers[i].size <= 124 fpga_config_buffers[i].size_written) { 125 fpga_config_buffers[i].write_requested = 0; 126 current_block++; 127 *buffer_addr_completed = 128 fpga_config_buffers[i].addr; 129 return 0; 130 } 131 } 132 } 133 134 return -1; 135 } 136 137 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 138 uint32_t *count) 139 { 140 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 141 *count = 0; 142 int resp_len = 0; 143 uint32_t resp[5]; 144 int all_completed = 1; 145 146 while (*count < 3) { 147 148 resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, 149 resp, sizeof(resp) / sizeof(resp[0])); 150 151 if (resp_len < 0) 152 break; 153 154 max_blocks++; 155 rcv_id++; 156 157 if (mark_last_buffer_xfer_completed( 158 &completed_addr[*count]) == 0) 159 *count = *count + 1; 160 else 161 break; 162 } 163 164 if (*count <= 0) { 165 if (resp_len != MBOX_NO_RESPONSE && 166 resp_len != MBOX_TIMEOUT && resp_len != 0) { 167 mailbox_clear_response(); 168 return INTEL_SIP_SMC_STATUS_ERROR; 169 } 170 171 *count = 0; 172 } 173 174 intel_fpga_sdm_write_all(); 175 176 if (*count > 0) 177 status = INTEL_SIP_SMC_STATUS_OK; 178 else if (*count == 0) 179 status = INTEL_SIP_SMC_STATUS_BUSY; 180 181 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 182 if (fpga_config_buffers[i].write_requested != 0) { 183 all_completed = 0; 184 break; 185 } 186 } 187 188 if (all_completed == 1) 189 return INTEL_SIP_SMC_STATUS_OK; 190 191 return status; 192 } 193 194 static int intel_fpga_config_start(uint32_t config_type) 195 { 196 uint32_t response[3]; 197 int status = 0; 198 199 mailbox_clear_response(); 200 201 mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); 202 203 status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, 204 response, sizeof(response) / sizeof(response[0])); 205 206 if (status < 0) 207 return status; 208 209 max_blocks = response[0]; 210 bytes_per_block = response[1]; 211 212 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 213 fpga_config_buffers[i].size = 0; 214 fpga_config_buffers[i].size_written = 0; 215 fpga_config_buffers[i].addr = 0; 216 fpga_config_buffers[i].write_requested = 0; 217 fpga_config_buffers[i].block_number = 0; 218 fpga_config_buffers[i].subblocks_sent = 0; 219 } 220 221 blocks_submitted = 0; 222 current_block = 0; 223 read_block = 0; 224 current_buffer = 0; 225 send_id = 0; 226 rcv_id = 0; 227 228 return 0; 229 } 230 231 static bool is_fpga_config_buffer_full(void) 232 { 233 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 234 if (!fpga_config_buffers[i].write_requested) 235 return false; 236 return true; 237 } 238 239 static bool is_address_in_ddr_range(uint64_t addr) 240 { 241 if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE) 242 return true; 243 244 return false; 245 } 246 247 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 248 { 249 int i; 250 251 intel_fpga_sdm_write_all(); 252 253 if (!is_address_in_ddr_range(mem) || 254 !is_address_in_ddr_range(mem + size) || 255 is_fpga_config_buffer_full()) 256 return INTEL_SIP_SMC_STATUS_REJECTED; 257 258 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 259 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 260 261 if (!fpga_config_buffers[j].write_requested) { 262 fpga_config_buffers[j].addr = mem; 263 fpga_config_buffers[j].size = size; 264 fpga_config_buffers[j].size_written = 0; 265 fpga_config_buffers[j].write_requested = 1; 266 fpga_config_buffers[j].block_number = 267 blocks_submitted++; 268 fpga_config_buffers[j].subblocks_sent = 0; 269 break; 270 } 271 } 272 273 if (is_fpga_config_buffer_full()) 274 return INTEL_SIP_SMC_STATUS_BUSY; 275 276 return INTEL_SIP_SMC_STATUS_OK; 277 } 278 279 static int is_out_of_sec_range(uint64_t reg_addr) 280 { 281 switch (reg_addr) { 282 case(0xF8011100): /* ECCCTRL1 */ 283 case(0xF8011104): /* ECCCTRL2 */ 284 case(0xF8011110): /* ERRINTEN */ 285 case(0xF8011114): /* ERRINTENS */ 286 case(0xF8011118): /* ERRINTENR */ 287 case(0xF801111C): /* INTMODE */ 288 case(0xF8011120): /* INTSTAT */ 289 case(0xF8011124): /* DIAGINTTEST */ 290 case(0xF801112C): /* DERRADDRA */ 291 case(0xFFD12028): /* SDMMCGRP_CTRL */ 292 case(0xFFD12044): /* EMAC0 */ 293 case(0xFFD12048): /* EMAC1 */ 294 case(0xFFD1204C): /* EMAC2 */ 295 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 296 case(0xFFD12094): /* ECC_INT_MASK_SET */ 297 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 298 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 299 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 300 case(0xFFD120C0): /* NOC_TIMEOUT */ 301 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 302 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 303 case(0xFFD120D0): /* NOC_IDLEACK */ 304 case(0xFFD120D4): /* NOC_IDLESTATUS */ 305 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 306 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 307 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 308 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 309 return 0; 310 311 default: 312 break; 313 } 314 315 return -1; 316 } 317 318 /* Secure register access */ 319 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 320 { 321 if (is_out_of_sec_range(reg_addr)) 322 return INTEL_SIP_SMC_STATUS_ERROR; 323 324 *retval = mmio_read_32(reg_addr); 325 326 return INTEL_SIP_SMC_STATUS_OK; 327 } 328 329 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 330 uint32_t *retval) 331 { 332 if (is_out_of_sec_range(reg_addr)) 333 return INTEL_SIP_SMC_STATUS_ERROR; 334 335 mmio_write_32(reg_addr, val); 336 337 return intel_secure_reg_read(reg_addr, retval); 338 } 339 340 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 341 uint32_t val, uint32_t *retval) 342 { 343 if (!intel_secure_reg_read(reg_addr, retval)) { 344 *retval &= ~mask; 345 *retval |= val; 346 return intel_secure_reg_write(reg_addr, *retval, retval); 347 } 348 349 return INTEL_SIP_SMC_STATUS_ERROR; 350 } 351 352 /* 353 * This function is responsible for handling all SiP calls from the NS world 354 */ 355 356 uintptr_t sip_smc_handler(uint32_t smc_fid, 357 u_register_t x1, 358 u_register_t x2, 359 u_register_t x3, 360 u_register_t x4, 361 void *cookie, 362 void *handle, 363 u_register_t flags) 364 { 365 uint32_t val = 0; 366 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 367 uint32_t completed_addr[3]; 368 uint32_t count = 0; 369 370 switch (smc_fid) { 371 case SIP_SVC_UID: 372 /* Return UID to the caller */ 373 SMC_UUID_RET(handle, intl_svc_uid); 374 375 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 376 status = intel_mailbox_fpga_config_isdone(x1); 377 SMC_RET4(handle, status, 0, 0, 0); 378 379 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 380 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 381 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 382 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 383 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 384 385 case INTEL_SIP_SMC_FPGA_CONFIG_START: 386 status = intel_fpga_config_start(x1); 387 SMC_RET4(handle, status, 0, 0, 0); 388 389 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 390 status = intel_fpga_config_write(x1, x2); 391 SMC_RET4(handle, status, 0, 0, 0); 392 393 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 394 status = intel_fpga_config_completed_write(completed_addr, 395 &count); 396 switch (count) { 397 case 1: 398 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 399 completed_addr[0], 0, 0); 400 401 case 2: 402 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 403 completed_addr[0], 404 completed_addr[1], 0); 405 406 case 3: 407 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 408 completed_addr[0], 409 completed_addr[1], 410 completed_addr[2]); 411 412 case 0: 413 SMC_RET4(handle, status, 0, 0, 0); 414 415 default: 416 mailbox_clear_response(); 417 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 418 } 419 420 case INTEL_SIP_SMC_REG_READ: 421 status = intel_secure_reg_read(x1, &val); 422 SMC_RET3(handle, status, val, x1); 423 424 case INTEL_SIP_SMC_REG_WRITE: 425 status = intel_secure_reg_write(x1, (uint32_t)x2, &val); 426 SMC_RET3(handle, status, val, x1); 427 428 case INTEL_SIP_SMC_REG_UPDATE: 429 status = intel_secure_reg_update(x1, (uint32_t)x2, 430 (uint32_t)x3, &val); 431 SMC_RET3(handle, status, val, x1); 432 433 default: 434 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 435 cookie, handle, flags); 436 } 437 } 438 439 DECLARE_RT_SVC( 440 socfpga_sip_svc, 441 OEN_SIP_START, 442 OEN_SIP_END, 443 SMC_TYPE_FAST, 444 NULL, 445 sip_smc_handler 446 ); 447 448 DECLARE_RT_SVC( 449 socfpga_sip_svc_std, 450 OEN_SIP_START, 451 OEN_SIP_END, 452 SMC_TYPE_YIELD, 453 NULL, 454 sip_smc_handler 455 ); 456