stingray: Fix board configuration typo.

Default board configuration was set to bcm958742k which is not present
in current codebase. This causes a default platform build to fail.
Changing to bcm95874

stingray: Fix board configuration typo.

Default board configuration was set to bcm958742k which is not present
in current codebase. This causes a default platform build to fail.
Changing to bcm958742t.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ie24f94ef0ef316ff56fe142df5de45d70ba93c28

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Merge "Fix MISRA C issues in BL1/BL2/BL31" into integration

Merge "xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()" into integration

Fix MISRA C issues in BL1/BL2/BL31

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable name

Fix MISRA C issues in BL1/BL2/BL31

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.

Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "arm_fpga: adapt to new way of including gicv3 files" into integration

arm_fpga: adapt to new way of including gicv3 files

with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fp

arm_fpga: adapt to new way of including gicv3 files

with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fpga platform.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63

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Merge "xlat lib v2: Add support to pass shareability attribute for normal memory region" into integration

Merge changes from topic "brcm_initial_support" into integration

* changes:
doc: brcm: Add documentation file for brcm stingray platform
drivers: Add SPI Nor flash support
drivers: Add iproc s

Merge changes from topic "brcm_initial_support" into integration

* changes:
doc: brcm: Add documentation file for brcm stingray platform
drivers: Add SPI Nor flash support
drivers: Add iproc spi driver
drivers: Add emmc driver for Broadcom platforms
Add BL31 support for Broadcom stingray platform
Add BL2 support for Broadcom stingray platform
Add bl31 support common across Broadcom platforms
Add bl2 setup code common across Broadcom platforms
drivers: Add support to retrieve plat_toc_flags

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xlat lib v2: Add support to pass shareability attribute for normal memory region

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. i

xlat lib v2: Add support to pass shareability attribute for normal memory region

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.

There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.

If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754

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doc: brcm: Add documentation file for brcm stingray platform

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: I5e2c1220e9694d6ba771cc90daa0e70e967eebe6

drivers: Add SPI Nor flash support

Add SPI Nor flash support

Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

drivers: Add iproc spi driver

Add iproc spi driver

Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

drivers: Add emmc driver for Broadcom platforms

Add emmc driver for Broadcom platforms

Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadco

drivers: Add emmc driver for Broadcom platforms

Add emmc driver for Broadcom platforms

Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

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Add BL31 support for Broadcom stingray platform

Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Add BL2 support for Broadcom stingray platform

Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Add bl31 support common across Broadcom platforms

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Ic1a392a633b447935fa3a7528326c97845f5b1bc

Merge "uniphier: define PLAT_XLAT_TABLES_DYNAMIC only for BL2" into integration

Merge changes from topic "sb/fconf" into integration

* changes:
Check for out-of-bound accesses in the platform io policies
Check for out-of-bound accesses in the CoT description

Add bl2 setup code common across Broadcom platforms

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Iabeaee35c22608c93945c8295bf70947b0f6049a

xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at bu

xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at build-time.
For example, BL31 runs at EL3, so unneeded code will be trimmed.

[before]

0000000000000000 <is_dcache_enabled>:
0: d5384240 mrs x0, currentel
4: 53020c00 ubfx w0, w0, #2, #2
8: 7100041f cmp w0, #0x1
c: 54000081 b.ne 1c <is_dcache_enabled+0x1c> // b.any
10: d5381000 mrs x0, sctlr_el1
14: 53020800 ubfx w0, w0, #2, #1
18: d65f03c0 ret
1c: 7100081f cmp w0, #0x2
20: 54000061 b.ne 2c <is_dcache_enabled+0x2c> // b.any
24: d53c1000 mrs x0, sctlr_el2
28: 17fffffb b 14 <is_dcache_enabled+0x14>
2c: d53e1000 mrs x0, sctlr_el3
30: 17fffff9 b 14 <is_dcache_enabled+0x14>

[after]

0000000000000000 <is_dcache_enabled>:
0: d53e1000 mrs x0, sctlr_el3
4: 53020800 ubfx w0, w0, #2, #1
8: d65f03c0 ret

Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge changes from topic "macro-cleanup" into integration

* changes:
plat: remove redundant =1 from -D option
Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS

Merge "cryptocell: add support for Cryptocell 713" into integration

Merge "Fix coverity defects found on the FPGA port." into integration

Check for out-of-bound accesses in the platform io policies

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound access

Check for out-of-bound accesses in the platform io policies

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Remove the assertion in plat_get_image_source(), which is now redundant.

Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Check for out-of-bound accesses in the CoT description

The chain of trust array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Change

Check for out-of-bound accesses in the CoT description

The chain of trust array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Change-Id: Ic5ea20e43cf8ca959bb7f9b60de7c0839b390add
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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