Merge "dts: stm32mp157c: fix etzpc node location in DTSI file" into integration

Merge "ti: k3: common: Implement stub system_off" into integration

Merge "Rename Cortex-Hercules to Cortex-A78" into integration

Merge "Rename Cortex Hercules Files to Cortex A78" into integration

dts: stm32mp157c: fix etzpc node location in DTSI file

Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded wh

dts: stm32mp157c: fix etzpc node location in DTSI file

Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded while
rebasing.

Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d
Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node")
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge "qemu/qemu_sbsa: increase size to handle fdt" into integration

qemu/qemu_sbsa: increase size to handle fdt

64KB was not enouth to handle fdt, bl2 shows
following error message.

"ERROR: Invalid Device Tree at 0x10000000000: error -3"

This patch increases the

qemu/qemu_sbsa: increase size to handle fdt

64KB was not enouth to handle fdt, bl2 shows
following error message.

"ERROR: Invalid Device Tree at 0x10000000000: error -3"

This patch increases the size to 1MB to address above error.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I0726a0cea95087175451da0dba7410acd27df808

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Merge "marvell: drivers: mochi: specify stream ID for SD/MMC" into integration

Merge changes from topic "stm32-etzpc" into integration

* changes:
plat/stm32mp1: sp_min relies on etzpc driver
dts: stm32mp157c: add etzpc node
drivers: introduce ST ETZPC driver

Merge changes from topic "jb/8.6-features" into integration

* changes:
Enable ARMv8.6-ECV Self-Synch when booting to EL2
Enable ARMv8.6-FGT when booting to EL2

plat/stm32mp1: sp_min relies on etzpc driver

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign b

plat/stm32mp1: sp_min relies on etzpc driver

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign both to secure world only.

Define stm32mp15 SoC identifiers for the platform specific DECPROT
instances.

Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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dts: stm32mp157c: add etzpc node

Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.

Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etie

dts: stm32mp157c: add etzpc node

Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.

Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: introduce ST ETZPC driver

ETZPC stands for Extended TrustZone Protection Controller. It is a
resource conditional access device. It is mainly based on Arm TZPC.

ST ETZPC exposes memory map

drivers: introduce ST ETZPC driver

ETZPC stands for Extended TrustZone Protection Controller. It is a
resource conditional access device. It is mainly based on Arm TZPC.

ST ETZPC exposes memory mapped DECPROT cells to set access permissions
to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some
of the SoC internal memories.

ST ETZPC exposes memory mapped TZMA cells to set access permissions
to some SoC internal memories.

Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570
Co-developed-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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marvell: drivers: mochi: specify stream ID for SD/MMC

This patch enables the stream ID for the SD/MMC
controllers via dedicated unit register. Thanks to this
change it is possible to configure prope

marvell: drivers: mochi: specify stream ID for SD/MMC

This patch enables the stream ID for the SD/MMC
controllers via dedicated unit register. Thanks to this
change it is possible to configure properly the
IOMMU in OS and use the SD/MMC interface in a guest
Virtual Machine.

Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>

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Merge "marvell: a8k: enable BL31 cache by default" into integration

marvell: a8k: enable BL31 cache by default

BL31_CACHE_DISABLE flag was introduced as a work-around
for the older SoC revisions. Since it is not relevant in the
newest versions, toggle it to be disab

marvell: a8k: enable BL31 cache by default

BL31_CACHE_DISABLE flag was introduced as a work-around
for the older SoC revisions. Since it is not relevant in the
newest versions, toggle it to be disabled by default.
One can still specify it by adding 'BL31_CACHE_DISABLE=1'
string to the build command.

Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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Enable ARMv8.6-ECV Self-Synch when booting to EL2

Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
sel

Enable ARMv8.6-ECV Self-Synch when booting to EL2

Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
control register to enable this extension when booting a hypervisor at EL2.

Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Enable ARMv8.6-FGT when booting to EL2

The Fine Grained Traps (FGT) architecture extension was added to aarch64 in
ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific
inst

Enable ARMv8.6-FGT when booting to EL2

The Fine Grained Traps (FGT) architecture extension was added to aarch64 in
ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific
instructions in a more fine grained manner, with an enable bit for each
instruction. This patch adds support for this extension by enabling the
extension when booting an hypervisor at EL2.

Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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xlat_tables_v2: add base table section name parameter for spm_mm

Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macr

xlat_tables_v2: add base table section name parameter for spm_mm

Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.

In the commit 363830df1c28e (xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.

This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.

Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

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Rename Cortex-Hercules to Cortex-A78

Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Rename Cortex Hercules Files to Cortex A78

This should allow git to easily track file moves

Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327

ti: k3: common: Make UART number configurable

This allows to build for k3-based boards that use a different UART as
console, such as the IOT2050 which requires K3_USART=1.

Signed-off-by: Jan Kiszka

ti: k3: common: Make UART number configurable

This allows to build for k3-based boards that use a different UART as
console, such as the IOT2050 which requires K3_USART=1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I7171f86c3cabae2c575b8fbeecef839b48bd109b

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Merge "drivers: stm32_reset adapt interface to timeout argument" into integration

Merge "TF-A: Fix BL31 linker script error" into integration

drivers: stm32_reset adapt interface to timeout argument

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

Wi

drivers: stm32_reset adapt interface to timeout argument

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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