1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 /* 23 * Placeholder variables for copying the arguments that have been passed to 24 * BL31 from BL2. 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 #if !RESET_TO_BL31 30 /* 31 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 35 #endif 36 37 /* Weak definitions may be overridden in specific ARM standard platform */ 38 #pragma weak bl31_early_platform_setup2 39 #pragma weak bl31_platform_setup 40 #pragma weak bl31_plat_arch_setup 41 #pragma weak bl31_plat_get_next_image_ep_info 42 43 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 44 BL31_START, \ 45 BL31_END - BL31_START, \ 46 MT_MEMORY | MT_RW | MT_SECURE) 47 #if RECLAIM_INIT_CODE 48 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 49 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_INIT_CODE_END); 50 51 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 52 BL_INIT_CODE_BASE, \ 53 BL_INIT_CODE_END \ 54 - BL_INIT_CODE_BASE, \ 55 MT_CODE | MT_SECURE) 56 #endif 57 58 #if SEPARATE_NOBITS_REGION 59 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 60 BL31_NOBITS_BASE, \ 61 BL31_NOBITS_LIMIT \ 62 - BL31_NOBITS_BASE, \ 63 MT_MEMORY | MT_RW | MT_SECURE) 64 65 #endif 66 /******************************************************************************* 67 * Return a pointer to the 'entry_point_info' structure of the next image for the 68 * security state specified. BL33 corresponds to the non-secure image type 69 * while BL32 corresponds to the secure image type. A NULL pointer is returned 70 * if the image does not exist. 71 ******************************************************************************/ 72 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 73 { 74 entry_point_info_t *next_image_info; 75 76 assert(sec_state_is_valid(type)); 77 next_image_info = (type == NON_SECURE) 78 ? &bl33_image_ep_info : &bl32_image_ep_info; 79 /* 80 * None of the images on the ARM development platforms can have 0x0 81 * as the entrypoint 82 */ 83 if (next_image_info->pc) 84 return next_image_info; 85 else 86 return NULL; 87 } 88 89 /******************************************************************************* 90 * Perform any BL31 early platform setup common to ARM standard platforms. 91 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 92 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 93 * done before the MMU is initialized so that the memory layout can be used 94 * while creating page tables. BL2 has flushed this information to memory, so 95 * we are guaranteed to pick up good data. 96 ******************************************************************************/ 97 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 98 uintptr_t hw_config, void *plat_params_from_bl2) 99 { 100 /* Initialize the console to provide early debug support */ 101 arm_console_boot_init(); 102 103 #if RESET_TO_BL31 104 /* There are no parameters from BL2 if BL31 is a reset vector */ 105 assert(from_bl2 == NULL); 106 assert(plat_params_from_bl2 == NULL); 107 108 # ifdef BL32_BASE 109 /* Populate entry point information for BL32 */ 110 SET_PARAM_HEAD(&bl32_image_ep_info, 111 PARAM_EP, 112 VERSION_1, 113 0); 114 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 115 bl32_image_ep_info.pc = BL32_BASE; 116 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 117 118 #if defined(SPD_spmd) 119 /* SPM (hafnium in secure world) expects SPM Core manifest base address 120 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 121 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 122 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 123 * keep it in the last page. 124 */ 125 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 126 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 127 #endif 128 129 # endif /* BL32_BASE */ 130 131 /* Populate entry point information for BL33 */ 132 SET_PARAM_HEAD(&bl33_image_ep_info, 133 PARAM_EP, 134 VERSION_1, 135 0); 136 /* 137 * Tell BL31 where the non-trusted software image 138 * is located and the entry state information 139 */ 140 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 141 142 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 143 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 144 145 #if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33) 146 /* 147 * Hafnium in normal world expects its manifest address in x0, which 148 * is loaded at base of DRAM. 149 */ 150 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 151 #endif 152 153 # if ARM_LINUX_KERNEL_AS_BL33 154 /* 155 * According to the file ``Documentation/arm64/booting.txt`` of the 156 * Linux kernel tree, Linux expects the physical address of the device 157 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 158 * must be 0. 159 */ 160 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 161 bl33_image_ep_info.args.arg1 = 0U; 162 bl33_image_ep_info.args.arg2 = 0U; 163 bl33_image_ep_info.args.arg3 = 0U; 164 # endif 165 166 #else /* RESET_TO_BL31 */ 167 168 /* 169 * In debug builds, we pass a special value in 'plat_params_from_bl2' 170 * to verify platform parameters from BL2 to BL31. 171 * In release builds, it's not used. 172 */ 173 assert(((unsigned long long)plat_params_from_bl2) == 174 ARM_BL31_PLAT_PARAM_VAL); 175 176 /* 177 * Check params passed from BL2 should not be NULL, 178 */ 179 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 180 assert(params_from_bl2 != NULL); 181 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 182 assert(params_from_bl2->h.version >= VERSION_2); 183 184 bl_params_node_t *bl_params = params_from_bl2->head; 185 186 /* 187 * Copy BL33 and BL32 (if present), entry point information. 188 * They are stored in Secure RAM, in BL2's address space. 189 */ 190 while (bl_params != NULL) { 191 if (bl_params->image_id == BL32_IMAGE_ID) 192 bl32_image_ep_info = *bl_params->ep_info; 193 194 if (bl_params->image_id == BL33_IMAGE_ID) 195 bl33_image_ep_info = *bl_params->ep_info; 196 197 bl_params = bl_params->next_params_info; 198 } 199 200 if (bl33_image_ep_info.pc == 0U) 201 panic(); 202 #endif /* RESET_TO_BL31 */ 203 } 204 205 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 206 u_register_t arg2, u_register_t arg3) 207 { 208 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 209 210 /* 211 * Initialize Interconnect for this cluster during cold boot. 212 * No need for locks as no other CPU is active. 213 */ 214 plat_arm_interconnect_init(); 215 216 /* 217 * Enable Interconnect coherency for the primary CPU's cluster. 218 * Earlier bootloader stages might already do this (e.g. Trusted 219 * Firmware's BL1 does it) but we can't assume so. There is no harm in 220 * executing this code twice anyway. 221 * Platform specific PSCI code will enable coherency for other 222 * clusters. 223 */ 224 plat_arm_interconnect_enter_coherency(); 225 } 226 227 /******************************************************************************* 228 * Perform any BL31 platform setup common to ARM standard platforms 229 ******************************************************************************/ 230 void arm_bl31_platform_setup(void) 231 { 232 /* Initialize the GIC driver, cpu and distributor interfaces */ 233 plat_arm_gic_driver_init(); 234 plat_arm_gic_init(); 235 236 #if RESET_TO_BL31 237 /* 238 * Do initial security configuration to allow DRAM/device access 239 * (if earlier BL has not already done so). 240 */ 241 plat_arm_security_setup(); 242 243 #if defined(PLAT_ARM_MEM_PROT_ADDR) 244 arm_nor_psci_do_dyn_mem_protect(); 245 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 246 247 #endif /* RESET_TO_BL31 */ 248 249 /* Enable and initialize the System level generic timer */ 250 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 251 CNTCR_FCREQ(0U) | CNTCR_EN); 252 253 /* Allow access to the System counter timer module */ 254 arm_configure_sys_timer(); 255 256 /* Initialize power controller before setting up topology */ 257 plat_arm_pwrc_setup(); 258 259 #if RAS_EXTENSION 260 ras_init(); 261 #endif 262 263 #if USE_DEBUGFS 264 debugfs_init(); 265 #endif /* USE_DEBUGFS */ 266 } 267 268 /******************************************************************************* 269 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 270 * standard platforms 271 * Perform BL31 platform setup 272 ******************************************************************************/ 273 void arm_bl31_plat_runtime_setup(void) 274 { 275 console_switch_state(CONSOLE_FLAG_RUNTIME); 276 277 /* Initialize the runtime console */ 278 arm_console_runtime_init(); 279 280 #if RECLAIM_INIT_CODE 281 arm_free_init_memory(); 282 #endif 283 284 #if PLAT_RO_XLAT_TABLES 285 arm_xlat_make_tables_readonly(); 286 #endif 287 } 288 289 #if RECLAIM_INIT_CODE 290 /* 291 * Zero out and make RW memory used to store image boot time code so it can 292 * be reclaimed during runtime 293 */ 294 void arm_free_init_memory(void) 295 { 296 int ret = xlat_change_mem_attributes(BL_INIT_CODE_BASE, 297 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 298 MT_RW_DATA); 299 300 if (ret != 0) { 301 ERROR("Could not reclaim initialization code"); 302 panic(); 303 } 304 } 305 #endif 306 307 void __init bl31_platform_setup(void) 308 { 309 arm_bl31_platform_setup(); 310 } 311 312 void bl31_plat_runtime_setup(void) 313 { 314 arm_bl31_plat_runtime_setup(); 315 } 316 317 /******************************************************************************* 318 * Perform the very early platform specific architectural setup shared between 319 * ARM standard platforms. This only does basic initialization. Later 320 * architectural setup (bl31_arch_setup()) does not do anything platform 321 * specific. 322 ******************************************************************************/ 323 void __init arm_bl31_plat_arch_setup(void) 324 { 325 const mmap_region_t bl_regions[] = { 326 MAP_BL31_TOTAL, 327 #if RECLAIM_INIT_CODE 328 MAP_BL_INIT_CODE, 329 #endif 330 #if SEPARATE_NOBITS_REGION 331 MAP_BL31_NOBITS, 332 #endif 333 ARM_MAP_BL_RO, 334 #if USE_ROMLIB 335 ARM_MAP_ROMLIB_CODE, 336 ARM_MAP_ROMLIB_DATA, 337 #endif 338 #if USE_COHERENT_MEM 339 ARM_MAP_BL_COHERENT_RAM, 340 #endif 341 {0} 342 }; 343 344 setup_page_tables(bl_regions, plat_arm_get_mmap()); 345 346 enable_mmu_el3(0); 347 348 arm_setup_romlib(); 349 } 350 351 void __init bl31_plat_arch_setup(void) 352 { 353 arm_bl31_plat_arch_setup(); 354 } 355