plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable

Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.

plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable

Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.

The variable was not updated, when it was deprecated in a8k_common.mk
in commit 613bbde09e48874658af5a00612fe2a0b0388523.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8

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Merge "arm_fpga: Fix MPIDR topology checks" into integration

Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared

Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared resources: define resource identifiers

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Merge "stm32mp1: introduce shared resources support" into integration

Merge "doc: Fix some broken links" into integration

Merge "Workaround for Neoverse N1 erratum 1800710" into integration

Merge "doc: RAS: fixing broken links" into integration

doc: Fix some broken links

Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will

doc: Fix some broken links

Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will be fixed in a future patch.

Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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doc: RAS: fixing broken links

There were some links in the file "ras.rst" which were broken, this
patch fixes all the broken links in this file.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com

doc: RAS: fixing broken links

There were some links in the file "ras.rst" which were broken, this
patch fixes all the broken links in this file.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d

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Merge "linker_script: move .rela.dyn section to bl_common.ld.h" into integration

Merge "plat/arm: Add assert for the valid address of dtb information" into integration

Merge "Fix makefile to build on a Windows host PC" into integration

Fix makefile to build on a Windows host PC

The TF-A firmware build system is capable of building on both Unix like
and Windows host PCs. The commit ID 7ff088 "Enable MTE support" updated
the Makefil

Fix makefile to build on a Windows host PC

The TF-A firmware build system is capable of building on both Unix like
and Windows host PCs. The commit ID 7ff088 "Enable MTE support" updated
the Makefile to conditionally enable the MTE support if the AArch64
architecture revision was greater than 8.5. However, the Makefile changes
were dependent on shell commands that are only available on unix shells,
resulting in build failures on a Windows host PC.

This patch fixes the Makefile by using a more portable approach for
comparing the architecture revision.

Change-Id: Icb56cbecd8af5b0b9056d105970ff4a6edd1755a
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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Merge "stm32mp1: disable neon in sp_min" into integration

Merge "stm32mp1: check stronger the secondary CPU entry point" into integration

plat/arm: Add assert for the valid address of dtb information

Added assert in the code to check valid address of dtb information
structure retrieved from fw_config device tree.
This patch fixes cove

plat/arm: Add assert for the valid address of dtb information

Added assert in the code to check valid address of dtb information
structure retrieved from fw_config device tree.
This patch fixes coverity defect:360213.

Also, removed conditional calling of "fconf_populate" as "fconf_populate"
function already checks the validity of the device tree address received
and go to panic in case of address is NULL.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib83e4e84a95e2456a12c7a2bb3fe70461d882cba

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Merge "allwinner: Disable NS access to PRCM power control registers" into integration

allwinner: Disable NS access to PRCM power control registers

The non-secure world has no business accessing the CPU power switches in
the PRCM; those are handled by TF-A or the SCP. Only allow acces

allwinner: Disable NS access to PRCM power control registers

The non-secure world has no business accessing the CPU power switches in
the PRCM; those are handled by TF-A or the SCP. Only allow access to the
clock control part of the PRCM.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I657b97f4ea8a0073448ad3343fbc66ba168ed89e

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uniphier: increase BL33 max size and GZIP temporary buffer size

The current BL33 size is large enough for U-Boot, but we need to
increase the limit to use other boot loaders such as edk2.

Increase

uniphier: increase BL33 max size and GZIP temporary buffer size

The current BL33 size is large enough for U-Boot, but we need to
increase the limit to use other boot loaders such as edk2.

Increase the buffer size used for GZIP decompression too.

BL33 max size (UNIPHIER_BL33_MAX_SIZE): 1MB -> 8MB
GZIP buffer (UNIPHIER_IMAGE_BUF_SIZE): 1MB -> 8MB

Increasing the block buffer size (UNIPHIER_BLOCK_BUF_SIZE) is not
required, but I increased it too to make it work more efficiently.

Change-Id: I4fa6d795bed9ab9ada7f8f616c7d47076139e3a8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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linker_script: move .rela.dyn section to bl_common.ld.h

The .rela.dyn section is the same for BL2-AT-EL3, BL31, TSP.

Move it to the common header file.

I slightly changed the definition so that we

linker_script: move .rela.dyn section to bl_common.ld.h

The .rela.dyn section is the same for BL2-AT-EL3, BL31, TSP.

Move it to the common header file.

I slightly changed the definition so that we can do "RELA_SECTION >RAM".
It still produced equivalent elf images.

Please note I got rid of '.' from the VMA field. Otherwise, if the end
of previous .data section is not 8-byte aligned, it fails to link.

aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes
aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes
aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes
make: *** [Makefile:1071: build/qemu/release/bl31/bl31.elf] Error 1

Change-Id: Iba7422d99c0374d4d9e97e6fd47bae129dba5cc9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Upgrade libfdt source files

This version corresponds to the following commit <7be250b>
libfdt: Correct condition for reordering blocks

Also, updated the Juno romlib jumptable with fdt APIs.

Change

Upgrade libfdt source files

This version corresponds to the following commit <7be250b>
libfdt: Correct condition for reordering blocks

Also, updated the Juno romlib jumptable with fdt APIs.

Change-Id: Ib6d28c1aea81c2144a263958f0792cc4daea7a1f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping th

Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping the entire LLC to SRAM
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
plat: marvell: armada: reduce memory size reserved for FIP image
plat: marvell: armada: platform definitions cleanup
plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
drivers: marvell: add CCU driver API for window state checking
drivers: marvell: align and extend llc macros
plat: marvell: a8k: move address config of cp1/2 to BL2
plat: marvell: armada: re-enable BL32_BASE definition
plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
marvell: comphy: initialize common phy selector for AP mode
marvell: comphy: update rx_training procedure
plat: marvell: armada: configure amb for all CPs
plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

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arm_fpga: Fix MPIDR topology checks

The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has
some issues, which leads to problems when matching GICv3 redistributors
with cores:
- The po

arm_fpga: Fix MPIDR topology checks

The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has
some issues, which leads to problems when matching GICv3 redistributors
with cores:
- The power domain tree was not taking multithreading into account, so
we ended up with the wrong mapping between MPIDRs and core IDs.
- Before even considering an MPIDR, we try to make sure Aff2 is 0.
Unfortunately this is the cluster ID when the MT bit is set.
- We mask off the MT bit in MPIDR, before basing decisions on it.
- When detecting the MT bit, we are properly calculating the thread ID,
but don't account for the shift in the core and cluster ID checks.

Those problems lead to early rejections of MPIDRs values, in particular
when called from the GIC code. As a result, CPU_ON for secondary cores
was failing for most of the cores.

Fix this by properly handling the MT bit in plat_core_pos_by_mpidr(),
also pulling in FPGA_MAX_PE_PER_CPU when populating the power domain
tree.

Change-Id: I71b2255fc0d27bfe5806511df479ab38e4e33fc4
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "fw_config_handoff" into integration

* changes:
doc: Update arg usage for BL2 and BL31 setup functions
doc: Update BL1 and BL2 boot flow
plat/arm: Use only fw_config b

Merge changes from topic "fw_config_handoff" into integration

* changes:
doc: Update arg usage for BL2 and BL31 setup functions
doc: Update BL1 and BL2 boot flow
plat/arm: Use only fw_config between bl2 and bl31

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doc: Update arg usage for BL2 and BL31 setup functions

Updated the porting guide for the usage of received arguments
in BL2 and BL32 setup functions in case of Arm platform.

Signed-off-by: Manish V

doc: Update arg usage for BL2 and BL31 setup functions

Updated the porting guide for the usage of received arguments
in BL2 and BL32 setup functions in case of Arm platform.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0

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