feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply

feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.

First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).

A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.

Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.

Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.

Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.

Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rse): fix iovec parameter check in rse comms

Allow NULL pointers as in/outvec pointer, but only if the
corresponding length is 0, in which case it is not used.
Introduce check for outvec as wel

feat(rse): fix iovec parameter check in rse comms

Allow NULL pointers as in/outvec pointer, but only if the
corresponding length is 0, in which case it is not used.
Introduce check for outvec as well, where NULL pointer
would cause illegal dereferencing on evaluation of
out_vec[0].base

Signed-off-by: Martin Fonai <martin.fonai@arm.com>
Change-Id: Ie5ea11ed63d942a063a9cfed8333b553b96e9924

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Merge "feat(cpus): add support for Rosillo cpu" into integration

Merge "fix(cpufeat): enable access to extended BRPs/WRPs" into integration

Merge changes I215a84bd,I83710d84 into integration

* changes:
perf(cpus): reduce the footprint of errata reporting
refactor(cpus): make errata reporting more generic

Merge changes from topic "upstream_ddr_reg_accesories" into integration

* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support

fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body

fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I71a1ad2a6f85edbf5133a7860453db2937988e22
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteratio

fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.
Used boolean in control expressions for fixing this violation.

MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.

Change-Id: Ic6536e1b749a7aacdf265c632ceea8d344f2e7b5
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The operand is explicitly typecasted to required type
to match the operand/return type.

Change-Id: I9d9a2e13225369281e2a1dc09d06bf6177d81f3a
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(build): assign the ldflags-common variable before appending to it

Otherwise the first value is lost, causing odd behaviours.

Change-Id: I6df892bf8f706db71d0aa7e67f5076cc9583e477
Signed-off-by:

fix(build): assign the ldflags-common variable before appending to it

Otherwise the first value is lost, causing odd behaviours.

Change-Id: I6df892bf8f706db71d0aa7e67f5076cc9583e477
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpus): add support for Rosillo cpu

Add basic CPU library code to support Rosillo CPU

Change-Id: I0e11e511511562297e4dccd2745842ebcfa2bff4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform" into integration

Merge "feat(el3-runtime): check the exception vector size" into integration

feat(el3-runtime): check the exception vector size

Currently, if the exception vector is too big it will fail with a
"Warning: repeat < 0; .fill ignored" error that is quite unclear. This
only happe

feat(el3-runtime): check the exception vector size

Currently, if the exception vector is too big it will fail with a
"Warning: repeat < 0; .fill ignored" error that is quite unclear. This
only happens when the vector entry is bigger than its allocated 128
bytes so add an explicit check with a descriptive message to ease
debugging when this happens.

Change-Id: I4f7acdcedab38bc96416dd0d0c6a8a60b7986e17
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesa

refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesas platforms.

Due to the above renaming, function console_renesas_register is duplicated
in both scif.h and console.h, so it should be removed from scif.h

Change-Id: I42b44d1786578f7ed8db34e7da421836ea60b5e2
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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Merge "fix(context-mgmt): actually clear MDCR_EL3 bits" into integration

Merge changes from topic "bk/simpler_panic" into integration

* changes:
refactor(aarch64): remove crash reporting's dependency on cpu_data
fix(el3-runtime): remove lower_el_panic()

Merge changes from topic "at/ras-rdaspen" into integration

* changes:
feat(rdaspen/ras): dump the CPER buffer contents
feat(rdaspen/ras): generate CPER at TF-A EL3
feat(rdaspen/ras): add DT bu

Merge changes from topic "at/ras-rdaspen" into integration

* changes:
feat(rdaspen/ras): dump the CPER buffer contents
feat(rdaspen/ras): generate CPER at TF-A EL3
feat(rdaspen/ras): add DT buffer and IRQ setup
feat(rdaspen): event handler for CPU RAS
feat(rdaspen/ras): intr RAS handling for PC CPU

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Merge "feat(rk3588): report actual measured PVTPLL clocks" into integration

fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1

Use ARM_FW_CONFIG_BASE and ARM_FW_CONFIG_MAX_SIZE instead of platform
macros PLAT_FW_CONFIG_BASE and PLAT_FW_CONFIG_MAX_SIZE w

fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1

Use ARM_FW_CONFIG_BASE and ARM_FW_CONFIG_MAX_SIZE instead of platform
macros PLAT_FW_CONFIG_BASE and PLAT_FW_CONFIG_MAX_SIZE when
RESET_TO_BL2 and ARM_FW_CONFIG_LOAD_ENABLE are set to 1.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I0848852250eba5a3328e25cbea4fff413f344327

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feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagou

feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Da

feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Data Entry
CPER CPU Error Section
- Arm Processor Error Record
- Arm Processor Error Information
- Arm Processor Context Information

Change-Id: I7e9703a69edec15cbb6f0522333700bb8d7007bf
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
S

feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>

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feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all i

feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all inband errors to be handled on AP according
to a CPU RAS event handler:

- Skips spurious entries – returns early when
`ERXSTATUS.{V|CE}` is already clear, disposing of queued phantom
interrupts.

- Clears the error record – rewrites `ERXSTATUS_EL1`, zeros
`ERXMISC0`, `PFG_CTL`, and `PFG_CDN`, then logs the post clear state
for firmware trace.

Inband errors only consist of:
- Corrected Errors
- Deferred Errors

- Change the RAS CPU intr handler logs from VERBOSE to WARN.

Change-Id: I7eb8fecb42095551f51c9d1c5752775f1b577970
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): intr RAS handling for PC CPU

This introduces and enables the RAS framework and enables
the RAS for CPU handling.

This commit ensures that RAS settings are initialized on
all CPU

feat(rdaspen/ras): intr RAS handling for PC CPU

This introduces and enables the RAS framework and enables
the RAS for CPU handling.

This commit ensures that RAS settings are initialized on
all CPU cores during the firmware boot stage. Previously,
the initialization for RAS processing was only done on
the primary CPU core.

This also introduces a custom bl31_platform_setup to
allow RAS specific intialisations.

Change-Id: Ia3258aed63b8994c53ec8cc49bd27d0d907e218e
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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