fix(sdei): ensure that interrupt ID is valid

As per SDEI spec (section 5.1.14.1), SDEI_INTERRUPT_BIND interface
expects a valid PPI or SPI. SGI's are not allowed to be bounded.
Current check in the

fix(sdei): ensure that interrupt ID is valid

As per SDEI spec (section 5.1.14.1), SDEI_INTERRUPT_BIND interface
expects a valid PPI or SPI. SGI's are not allowed to be bounded.
Current check in the code only checks for an SGI and returns invalid
ID. This check is insufficient as it will not catch architecturally
invalid interrupt IDs.

Modify the check to ensure that interrupt is either PPI or SPI.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I52eb0a6d7f88a12f6816cff9b68fb3a7ca12cbb7

show more ...

Merge "refactor(cm): move EL3 registers to global context" into integration

refactor(cm): move EL3 registers to global context

Currently, EL3 context registers are duplicated per-world per-cpu.
Some registers have the same value across all CPUs, so this patch
moves these re

refactor(cm): move EL3 registers to global context

Currently, EL3 context registers are duplicated per-world per-cpu.
Some registers have the same value across all CPUs, so this patch
moves these registers out into a per-world context to reduce
memory usage.

Change-Id: I91294e3d5f4af21a58c23599af2bdbd2a747c54a
Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

show more ...

Merge "feat(rmm): update RMI VERSION command as per EAC5" into integration

feat(rmm): update RMI VERSION command as per EAC5

This patch adds necessary support for RMI_VERSION command.
This patch sets RMI version numbers to 1.0 as per
RMM Specification 1.0-eac5.

Change-Id:

feat(rmm): update RMI VERSION command as per EAC5

This patch adds necessary support for RMI_VERSION command.
This patch sets RMI version numbers to 1.0 as per
RMM Specification 1.0-eac5.

Change-Id: If7f88d5b5efa58716752488108fa110fc71ae836
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

show more ...

Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update

Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update the neoverse-N1 errata ABI struct
fix(cpus): fix the rev-var of Cortex-X2
fix(errata-abi): update the Cortex-A78C errata ABI struct
fix(cpus): update the rev-var for Cortex-A78AE
fix(errata-abi): update the Cortex-A76 errata ABI struct
fix(cpus): fix the rev-var for Cortex-A710

show more ...

Merge "fix(spmd): fix FFA_VERSION forwarding" into integration

fix(spmd): fix FFA_VERSION forwarding

When FFA_VERSION is forwarded from SPMD to SPMC, ensure that the full
NS GP regs context incl. x8-x17 is carried when building the SPMD to
SPMC direct message.

fix(spmd): fix FFA_VERSION forwarding

When FFA_VERSION is forwarded from SPMD to SPMC, ensure that the full
NS GP regs context incl. x8-x17 is carried when building the SPMD to
SPMC direct message.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3467c0e04de95ab80f7c86a0763021a5fa961e4d

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2080326

Cortex-A510 erratum 2080326 is a Cat B erratum that applies
to all revisions <= r0p2 and is fixed in r0p3.
The workaround sequence helps perform

fix(cpus): workaround for Cortex-A510 erratum 2080326

Cortex-A510 erratum 2080326 is a Cat B erratum that applies
to all revisions <= r0p2 and is fixed in r0p3.
The workaround sequence helps perform a DSB after each TLBI
instruction and can be applied only for version r0p2 and has
minimal performance impact.
The workaround is not applicable for versions < r0p2.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873361/latest

Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the lat

fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(errata-abi): update the Neoverse-N2 errata ABI struct

Updated the structure for Neoverse_N2 in the errata ABI file
for the missing entries from the neoverse_n2.S file.

Change-Id: I635c39014a7b3

fix(errata-abi): update the Neoverse-N2 errata ABI struct

Updated the structure for Neoverse_N2 in the errata ABI file
for the missing entries from the neoverse_n2.S file.

Change-Id: I635c39014a7b3e842a978a59e122d508d4bcf3c1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(errata-abi): update the neoverse-N1 errata ABI struct

Updated the structure for Neoverse_N1 in the errata ABI file
for the missing entries from the neoverse_n1.S file.

Change-Id: I79a1a72b80778

fix(errata-abi): update the neoverse-N1 errata ABI struct

Updated the structure for Neoverse_N1 in the errata ABI file
for the missing entries from the neoverse_n1.S file.

Change-Id: I79a1a72b807781d65a6afc9e0367e77b21eecf41
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(cpus): fix the rev-var of Cortex-X2

Update the revision and variant information in the
errata ABI file, cortex_X2.S file for erratum ID - 2058056
to match the revision and variant in the latest

fix(cpus): fix the rev-var of Cortex-X2

Update the revision and variant information in the
errata ABI file, cortex_X2.S file for erratum ID - 2058056
to match the revision and variant in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I28ee39949d977c53d6f5243100f0c29bc3c0428c
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(errata-abi): update the Cortex-A78C errata ABI struct

Updated the structure for Cortex-A78C in the errata ABI file
for missing entries from the cortex_a78c.S file.

Change-Id: I3d994337221de0326

fix(errata-abi): update the Cortex-A78C errata ABI struct

Updated the structure for Cortex-A78C in the errata ABI file
for missing entries from the cortex_a78c.S file.

Change-Id: I3d994337221de03264be235f1727de7494ed4312
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(cpus): update the rev-var for Cortex-A78AE

Update the revision and variant information in the
cortex_a78_ae.s and errata ABI file for erratum ID - 2376748
based on the latest SDEN.

SDEN documen

fix(cpus): update the rev-var for Cortex-A78AE

Update the revision and variant information in the
cortex_a78_ae.s and errata ABI file for erratum ID - 2376748
based on the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I082aac41adf717b0d5d59046a8933a3f5a3de94f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(errata-abi): update the Cortex-A76 errata ABI struct

Updated the structure for Cortex-A76 in the errata ABI file
for the missing entries from the cortex_a76.S file.

Change-Id: Iceaf26fb2de493a8

fix(errata-abi): update the Cortex-A76 errata ABI struct

Updated the structure for Cortex-A76 in the errata ABI file
for the missing entries from the cortex_a76.S file.

Change-Id: Iceaf26fb2de493a877c4c100c0137f9255fc8b9f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

fix(cpus): fix the rev-var for Cortex-A710

Update the revision and variant information in the
errata ABI file, cortex_A710.S file for erratum ID - 2058056
and erratum ID - 2055002 to match the revis

fix(cpus): fix the rev-var for Cortex-A710

Update the revision and variant information in the
errata ABI file, cortex_A710.S file for erratum ID - 2058056
and erratum ID - 2055002 to match the revision and variant
in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Ie010dae90dabf8670f588a06f9a606cf41e22afa
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

feat(spm): separate StMM SP specifics to add support for a S-EL0 SP

This patch separates the code from SPM_MM to get xlat table context and
move it to a common location. In addition, only APIs requi

feat(spm): separate StMM SP specifics to add support for a S-EL0 SP

This patch separates the code from SPM_MM to get xlat table context and
move it to a common location. In addition, only APIs required from both
SPM_MM and FF-A EL3 SPMC are moved to the common location.

This allows understanding better what is required to support a S-EL0 SP
instead of trying to retrofit what already exists.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I142d7fbef5239869176d0de93842c66051d7ed78

show more ...

refactor(spm-mm): reorganize secure partition manager shim code

In preparation for adding the support for SEL0 SP in EL3 SPMC,
restructure the existing SPM_MM shim code in a way that allows reuse
of

refactor(spm-mm): reorganize secure partition manager shim code

In preparation for adding the support for SEL0 SP in EL3 SPMC,
restructure the existing SPM_MM shim code in a way that allows reuse
of the code for both SPM_MM interface and FF-A EL3 SPMC interface. The
code for changing exception levels is identical for both.

With this restructuring of the code, the shim exception code is moved to
the common sub-directory.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iadda9cf73f12b56e6a1d31fc21b5ba5dc355867f

show more ...

fix(cpus): workaround for Cortex-X3 erratum 2070301

Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001

fix(cpus): workaround for Cortex-X3 erratum 2070301

Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

feat(rmmd): pass SMCCCv1.3 SVE hint bit to RMM

SMCCCv1.3 introduces SVE hint bit that denotes the absence of SVE
specific live state. Update the SMC function ID with SVE hint bit if it
is set the fl

feat(rmmd): pass SMCCCv1.3 SVE hint bit to RMM

SMCCCv1.3 introduces SVE hint bit that denotes the absence of SVE
specific live state. Update the SMC function ID with SVE hint bit if it
is set the flags and pass it to RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ibb1d73440ed1e2283a103cfd2c4592be5d3a74cb

show more ...

Merge "feat(rmmd): enable SME for RMM" into integration

feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use

feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use FPU or SVE.

The Relevant RMM support can be found here :
https://github.com/TF-RMM/tf-rmm/commit/0ccd7ae58b00

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I3bbdb840e7736dec00b71c85fcec3d5719413ffd

show more ...

fix(spmd): coverity scan issues

Coverity defects fixed by this patch are:
*** CID 400208: Performance inefficiencies (PASS_BY_VALUE)
/include/services/el3_spmd_logical_sp.h: 108 in
ffa_partition_i

fix(spmd): coverity scan issues

Coverity defects fixed by this patch are:
*** CID 400208: Performance inefficiencies (PASS_BY_VALUE)
/include/services/el3_spmd_logical_sp.h: 108 in
ffa_partition_info_regs_get_last_idx()

*** CID 400207: Performance inefficiencies (PASS_BY_VALUE)
/services/std_svc/spmd/spmd_logical_sp.c: 359 in
ffa_partition_info_regs_get_part_info()

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9597377a8ec3d5519995e1619d99ee7102f33939

show more ...

Merge "fix(errata-abi): fix the rev-var for Cortex-A710" into integration