Tegra: public interfaces to get the chip's major/minor versions

This patch opens up the interfaces to read the chip's major/minor versions
for all Tegra drivers to use.

Signed-off-by: Varun Wadekar

Tegra: public interfaces to get the chip's major/minor versions

This patch opens up the interfaces to read the chip's major/minor versions
for all Tegra drivers to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Move plat/common source file definitions to generic Makefiles

These source file definitions should be defined in generic
Makefiles so that all platforms can benefit. Ensure that the
symbols are prop

Move plat/common source file definitions to generic Makefiles

These source file definitions should be defined in generic
Makefiles so that all platforms can benefit. Ensure that the
symbols are properly marked as weak so they can be overridden
by platforms.

NOTE: This change is a potential compatibility break for
non-upstream platforms.

Change-Id: I7b892efa9f2d6d216931360dc6c436e1d10cffed
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

show more ...

plat/tegra: Enable Cortex-A53 erratum 855873 workaround

The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this er

plat/tegra: Enable Cortex-A53 erratum 855873 workaround

The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this erratum.

Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

plat/mediatek: Enable Cortex-A53 erratum 855873 workaround

The Mediatek 8173 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this er

plat/mediatek: Enable Cortex-A53 erratum 855873 workaround

The Mediatek 8173 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this erratum.

Change-Id: I6e1c7822c320d81bdd46b8942d1d755883dac1f5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Add workaround for ARM Cortex-A53 erratum 855873

ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and

Add workaround for ARM Cortex-A53 erratum 855873

ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.

Enable the workaround for the Juno boards.

Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge pull request #861 from soby-mathew/sm/aarch32_fixes

Misc AArch32 fixes

Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat

Introduce version 2 of the translation tables library

ARM platforms: Enable xlat tables lib v2

Modify ARM common makefile to use version 2 of the translation tables
library and include the new header in C files.

Simplify header dependencies related to

ARM platforms: Enable xlat tables lib v2

Modify ARM common makefile to use version 2 of the translation tables
library and include the new header in C files.

Simplify header dependencies related to this library to simplify the
change.

The following table contains information about the size increase in
bytes for BL1 after applying this patch. The code has been compiled for
different configurations of FVP in AArch64 mode with compiler GCC 4.9.3
20150413. The sizes have been calculated with the output of `nm` by
adding the size of all regions and comparing the total size before and
after the change. They are sumarized in the table below:

text bss data total
Release +660 -20 +88 +728
Debug +740 -20 +242 +962
Debug (LOG_LEVEL=50) +1120 -20 +317 +1417

Change-Id: I539e307f158ab71e3a8b771640001fc1bf431b29
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Apply workaround for errata 813419 of Cortex-A57

TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI tw

Apply workaround for errata 813419 of Cortex-A57

TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.

Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.

This errata has been enabled for Juno.

The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.

Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Simplify translation tables headers dependencies

The files affected by this patch don't really depend on `xlat_tables.h`.
By changing the included file it becomes easier to switch between the
two ve

Simplify translation tables headers dependencies

The files affected by this patch don't really depend on `xlat_tables.h`.
By changing the included file it becomes easier to switch between the
two versions of the translation tables library.

Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826

Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Merge pull request #863 from vwadekar/tegra-changes-from-downstream-v4

Tegra changes from downstream v4

Merge pull request #854 from rockchip-linux/pm_plat

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Tegra: enable SEPARATE_CODE_AND_RODATA build flag

This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the c

Tegra: enable SEPARATE_CODE_AND_RODATA build flag

This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the code.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

rockchip: Change the callback implement of power domain for rk3368

Change-Id: I6d39b4cac9b34b1f841e9bbddaf9c49785ba0c5e
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

Tegra210: assert if afflvl0/1 have incorrect state-ids

The linux kernel v3.10 does not use System Suspend function ID, whereas
v4.4 uses it. This means affinity levels 0/1 will have different state

Tegra210: assert if afflvl0/1 have incorrect state-ids

The linux kernel v3.10 does not use System Suspend function ID, whereas
v4.4 uses it. This means affinity levels 0/1 will have different state id
values during System Suspend entry. This patch updates the assert criteria
to check both the state id values.

Change-Id: I07fcaf99501cc9622e40d0a2c1eb4a4a160be10a
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: SiP: 64-bit address for Video Memory base

This patch allows the NS world to pass 64-bit base address for
the Video Memory carveout region.

Change-Id: I7e47cc1f5425bd39c6763755b801517013e1e0c

Tegra: SiP: 64-bit address for Video Memory base

This patch allows the NS world to pass 64-bit base address for
the Video Memory carveout region.

Change-Id: I7e47cc1f5425bd39c6763755b801517013e1e0cd
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: increase ADDR_SPACE_SIZE to 35 bits

This patch increases the ADDR_SPACE_SIZE macro (virtual address)
to 35 bits, to support max memory of 32G, for all Tegra platforms.

Change-Id: I8e6861601d

Tegra: increase ADDR_SPACE_SIZE to 35 bits

This patch increases the ADDR_SPACE_SIZE macro (virtual address)
to 35 bits, to support max memory of 32G, for all Tegra platforms.

Change-Id: I8e6861601d3a667d7428988c7596b0adebfa0548
Signed-off-by: Steven kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: init the console only if the platform supports it

Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling

Tegra: init the console only if the platform supports it

Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling console_init().

Change-Id: Icc9c59cb979d91fd0a72e4732403b3284bdd2dfc
Signed-off-by: Damon Duan <danield@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra210: new TZDRAM base address

This patch modifies the TZDRAM base address to the new aperture
allocated by the bootloader.

Change-Id: Id158d15b1ec9aa681136d258e90fbba930aebf92
Signed-off-by: Va

Tegra210: new TZDRAM base address

This patch modifies the TZDRAM base address to the new aperture
allocated by the bootloader.

Change-Id: Id158d15b1ec9aa681136d258e90fbba930aebf92
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra210: set core power state during cluster power down

This patch sets the core power state during cluster power down,
so that the 'get_target_pwr_state' handler can calculate the
proper states fo

Tegra210: set core power state during cluster power down

This patch sets the core power state during cluster power down,
so that the 'get_target_pwr_state' handler can calculate the
proper states for all the affinity levels.

Change-Id: If4adb001011208916427ee1623c6c923bed99985
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: calculate proper power state for affinity levels

This patch fixes the 'tegra_soc_get_target_pwr_state' handler used to
calculate the proper state for each of the affinity levels.

Change-Id:

Tegra: calculate proper power state for affinity levels

This patch fixes the 'tegra_soc_get_target_pwr_state' handler used to
calculate the proper state for each of the affinity levels.

Change-Id: Id16bd15b96f0fc633ffeac2d7a390592fbd0454b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: fix logic to calculate GICD_ISPENDR register address

This patch uses GICD_BASE to calculate the GICD_ISPENDR regsiter address
in the platform's 'plat_crash_print_regs' routine.

Reported by:

Tegra: fix logic to calculate GICD_ISPENDR register address

This patch uses GICD_BASE to calculate the GICD_ISPENDR regsiter address
in the platform's 'plat_crash_print_regs' routine.

Reported by: Seth Eatinger <seatinger@nvidia.com>

Change-Id: Ic7be29abc781f475ad25b59582ae60a0a2497377
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: uninit and re-init console across System Suspend

This patch removes the console_init() from runtime_setup() as we already
initialize it earlier and disables/enables it across "System Suspend"

Tegra: uninit and re-init console across System Suspend

This patch removes the console_init() from runtime_setup() as we already
initialize it earlier and disables/enables it across "System Suspend".

Change-Id: I992d3ca56ff4797faf83e8d7fa52c0ef3e1c3367
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: support for silicon/simulation platforms

This patch adds support to identify the underlying platform
on which we are running. The currently supported platforms
are actual silicon and simulati

Tegra: support for silicon/simulation platforms

This patch adds support to identify the underlying platform
on which we are running. The currently supported platforms
are actual silicon and simulation platforms.

Change-Id: Iadf96e79ec663b3dbd1a18e9bb95ffcdb82fc8af
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...