1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context.h> 35 #include <context_mgmt.h> 36 #include <console.h> 37 #include <debug.h> 38 #include <memctrl.h> 39 #include <mmio.h> 40 #include <platform.h> 41 #include <platform_def.h> 42 #include <pmc.h> 43 #include <psci.h> 44 #include <tegra_def.h> 45 #include <tegra_private.h> 46 47 extern uint64_t tegra_bl31_phys_base; 48 extern uint64_t tegra_sec_entry_point; 49 extern uint64_t tegra_console_base; 50 51 /* 52 * The following platform setup functions are weakly defined. They 53 * provide typical implementations that will be overridden by a SoC. 54 */ 55 #pragma weak tegra_soc_pwr_domain_suspend 56 #pragma weak tegra_soc_pwr_domain_on 57 #pragma weak tegra_soc_pwr_domain_off 58 #pragma weak tegra_soc_pwr_domain_on_finish 59 #pragma weak tegra_soc_pwr_domain_power_down_wfi 60 #pragma weak tegra_soc_prepare_system_reset 61 #pragma weak tegra_soc_prepare_system_off 62 #pragma weak tegra_soc_get_target_pwr_state 63 64 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 65 { 66 return PSCI_E_NOT_SUPPORTED; 67 } 68 69 int tegra_soc_pwr_domain_on(u_register_t mpidr) 70 { 71 return PSCI_E_SUCCESS; 72 } 73 74 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 75 { 76 return PSCI_E_SUCCESS; 77 } 78 79 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 80 { 81 return PSCI_E_SUCCESS; 82 } 83 84 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 85 { 86 return PSCI_E_SUCCESS; 87 } 88 89 int tegra_soc_prepare_system_reset(void) 90 { 91 return PSCI_E_SUCCESS; 92 } 93 94 __dead2 void tegra_soc_prepare_system_off(void) 95 { 96 ERROR("Tegra System Off: operation not handled.\n"); 97 panic(); 98 } 99 100 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 101 const plat_local_state_t *states, 102 unsigned int ncpu) 103 { 104 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; 105 106 assert(ncpu); 107 108 do { 109 temp = *states++; 110 if ((temp < target)) 111 target = temp; 112 } while (--ncpu); 113 114 return target; 115 } 116 117 /******************************************************************************* 118 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 119 * call to get the `power_state` parameter. This allows the platform to encode 120 * the appropriate State-ID field within the `power_state` parameter which can 121 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 122 ******************************************************************************/ 123 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) 124 { 125 /* all affinities use system suspend state id */ 126 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 127 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; 128 } 129 130 /******************************************************************************* 131 * Handler called when an affinity instance is about to enter standby. 132 ******************************************************************************/ 133 void tegra_cpu_standby(plat_local_state_t cpu_state) 134 { 135 /* 136 * Enter standby state 137 * dsb is good practice before using wfi to enter low power states 138 */ 139 dsb(); 140 wfi(); 141 } 142 143 /******************************************************************************* 144 * Handler called when an affinity instance is about to be turned on. The 145 * level and mpidr determine the affinity instance. 146 ******************************************************************************/ 147 int tegra_pwr_domain_on(u_register_t mpidr) 148 { 149 return tegra_soc_pwr_domain_on(mpidr); 150 } 151 152 /******************************************************************************* 153 * Handler called when a power domain is about to be turned off. The 154 * target_state encodes the power state that each level should transition to. 155 ******************************************************************************/ 156 void tegra_pwr_domain_off(const psci_power_state_t *target_state) 157 { 158 tegra_soc_pwr_domain_off(target_state); 159 } 160 161 /******************************************************************************* 162 * Handler called when a power domain is about to be suspended. The 163 * target_state encodes the power state that each level should transition to. 164 ******************************************************************************/ 165 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) 166 { 167 tegra_soc_pwr_domain_suspend(target_state); 168 169 /* Disable console if we are entering deep sleep. */ 170 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 171 PSTATE_ID_SOC_POWERDN) 172 console_uninit(); 173 174 /* disable GICC */ 175 tegra_gic_cpuif_deactivate(); 176 } 177 178 /******************************************************************************* 179 * Handler called at the end of the power domain suspend sequence. The 180 * target_state encodes the power state that each level should transition to. 181 ******************************************************************************/ 182 __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t 183 *target_state) 184 { 185 /* call the chip's power down handler */ 186 tegra_soc_pwr_domain_power_down_wfi(target_state); 187 188 /* enter power down state */ 189 wfi(); 190 191 /* we can never reach here */ 192 ERROR("%s: operation not handled.\n", __func__); 193 panic(); 194 } 195 196 /******************************************************************************* 197 * Handler called when a power domain has just been powered on after 198 * being turned off earlier. The target_state encodes the low power state that 199 * each level has woken up from. 200 ******************************************************************************/ 201 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) 202 { 203 plat_params_from_bl2_t *plat_params; 204 205 /* 206 * Initialize the GIC cpu and distributor interfaces 207 */ 208 plat_gic_setup(); 209 210 /* 211 * Check if we are exiting from deep sleep. 212 */ 213 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 214 PSTATE_ID_SOC_POWERDN) { 215 216 /* Initialize the runtime console */ 217 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 218 TEGRA_CONSOLE_BAUDRATE); 219 220 /* 221 * Restore Memory Controller settings as it loses state 222 * during system suspend. 223 */ 224 tegra_memctrl_restore_settings(); 225 226 /* 227 * Security configuration to allow DRAM/device access. 228 */ 229 plat_params = bl31_get_plat_params(); 230 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 231 plat_params->tzdram_size); 232 233 /* 234 * Set up the TZRAM memory aperture to allow only secure world 235 * access 236 */ 237 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 238 } 239 240 /* 241 * Reset hardware settings. 242 */ 243 tegra_soc_pwr_domain_on_finish(target_state); 244 } 245 246 /******************************************************************************* 247 * Handler called when a power domain has just been powered on after 248 * having been suspended earlier. The target_state encodes the low power state 249 * that each level has woken up from. 250 ******************************************************************************/ 251 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 252 { 253 tegra_pwr_domain_on_finish(target_state); 254 } 255 256 /******************************************************************************* 257 * Handler called when the system wants to be powered off 258 ******************************************************************************/ 259 __dead2 void tegra_system_off(void) 260 { 261 INFO("Powering down system...\n"); 262 263 tegra_soc_prepare_system_off(); 264 } 265 266 /******************************************************************************* 267 * Handler called when the system wants to be restarted. 268 ******************************************************************************/ 269 __dead2 void tegra_system_reset(void) 270 { 271 INFO("Restarting system...\n"); 272 273 /* per-SoC system reset handler */ 274 tegra_soc_prepare_system_reset(); 275 276 /* 277 * Program the PMC in order to restart the system. 278 */ 279 tegra_pmc_system_reset(); 280 } 281 282 /******************************************************************************* 283 * Handler called to check the validity of the power state parameter. 284 ******************************************************************************/ 285 int32_t tegra_validate_power_state(unsigned int power_state, 286 psci_power_state_t *req_state) 287 { 288 assert(req_state); 289 290 return tegra_soc_validate_power_state(power_state, req_state); 291 } 292 293 /******************************************************************************* 294 * Platform handler called to check the validity of the non secure entrypoint. 295 ******************************************************************************/ 296 int tegra_validate_ns_entrypoint(uintptr_t entrypoint) 297 { 298 /* 299 * Check if the non secure entrypoint lies within the non 300 * secure DRAM. 301 */ 302 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) 303 return PSCI_E_SUCCESS; 304 305 return PSCI_E_INVALID_ADDRESS; 306 } 307 308 /******************************************************************************* 309 * Export the platform handlers to enable psci to invoke them 310 ******************************************************************************/ 311 static const plat_psci_ops_t tegra_plat_psci_ops = { 312 .cpu_standby = tegra_cpu_standby, 313 .pwr_domain_on = tegra_pwr_domain_on, 314 .pwr_domain_off = tegra_pwr_domain_off, 315 .pwr_domain_suspend = tegra_pwr_domain_suspend, 316 .pwr_domain_on_finish = tegra_pwr_domain_on_finish, 317 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, 318 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, 319 .system_off = tegra_system_off, 320 .system_reset = tegra_system_reset, 321 .validate_power_state = tegra_validate_power_state, 322 .validate_ns_entrypoint = tegra_validate_ns_entrypoint, 323 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, 324 }; 325 326 /******************************************************************************* 327 * Export the platform specific power ops and initialize Power Controller 328 ******************************************************************************/ 329 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 330 const plat_psci_ops_t **psci_ops) 331 { 332 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; 333 334 /* 335 * Flush entrypoint variable to PoC since it will be 336 * accessed after a reset with the caches turned off. 337 */ 338 tegra_sec_entry_point = sec_entrypoint; 339 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); 340 341 /* 342 * Reset hardware settings. 343 */ 344 tegra_soc_pwr_domain_on_finish(&target_state); 345 346 /* 347 * Initialize PSCI ops struct 348 */ 349 *psci_ops = &tegra_plat_psci_ops; 350 351 return 0; 352 } 353 354 /******************************************************************************* 355 * Platform handler to calculate the proper target power level at the 356 * specified affinity level 357 ******************************************************************************/ 358 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 359 const plat_local_state_t *states, 360 unsigned int ncpu) 361 { 362 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); 363 } 364