| b32e6b2b | 05-Jun-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #963 from soby-mathew/sm/scmi_dev
Add SCMI power domain and system power protocol support |
| c66f4ade | 05-Jun-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #961 from jeenu-arm/gic-600
Introduce ARM GIC-600 driver |
| 03dd6391 | 05-Jun-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #960 from jeenu-arm/cpu-libs
Add support for Cortex-A75 and Cortex-A55 CPUs |
| 40111d44 | 14-Nov-2016 |
Soby Mathew <soby.mathew@arm.com> |
Add SCMI support for Juno platform
This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_ma
Add SCMI support for Juno platform
This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_map` array.
Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| c04a3b6c | 14-Nov-2016 |
Soby Mathew <soby.mathew@arm.com> |
CSS: Add SCMI driver for SCP
This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented
CSS: Add SCMI driver for SCP
This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented in the driver. The SCP power management
abstraction layer for SCMI for CSS power management is also added.
A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI
driver over SCPI.
[1] ARM System Control and Management Interface v1.0 (SCMI)
Document number: ARM DEN 0056A
Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| e1c59ab3 | 06-Dec-2016 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Introduce ARM GIC-600 driver
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed t
Introduce ARM GIC-600 driver
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.
The driver provides APIs for Redistributor power management, and
overrides those in the generic GICv3 driver. The driver data is shared
between generic GICv3 driver and that of GIC-600.
For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER
is set to FVP_GIC600. Also update user guide.
Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| d40ab484 | 09-Nov-2016 |
David Wang <david.wang@arm.com> |
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardwa
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.
Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 0ceb3e1e | 01-Jun-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #957 from hzhuang1/finish_hikey_psci
Finish hikey psci |
| 1e54813a | 27-May-2017 |
Leo Yan <leo.yan@linaro.org> |
hikey: pm: finish PSCI hook functions
This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
S
hikey: pm: finish PSCI hook functions
This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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| c78d524c | 27-May-2017 |
Leo Yan <leo.yan@linaro.org> |
hikey: bl31: enable CCI port for cluster 0
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
hikey: bl31: enable CCI port for cluster 0
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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| a63db3ec | 27-May-2017 |
Leo Yan <leo.yan@linaro.org> |
hikey: fix for CPU topology
Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.
Signed-off-by: Leo Yan <leo.yan@l
hikey: fix for CPU topology
Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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|
| 22db0167 | 31-May-2017 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: fix uninitialized variable in ddr code
Fix uninitliazed variable in ddr driver code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> |
| 572e1413 | 30-May-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memory
Reduce code size when building with Trusted Board Boot enabled |
| 127793da | 24-May-2017 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: support BL31
Support BL31 and PSCI. Enable multiple cores in PSCI.
Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-b
hikey: support BL31
Support BL31 and PSCI. Enable multiple cores in PSCI.
Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
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| 32e9fc1a | 24-May-2017 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: support BL2
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2
is the mcu firmware that is used to scale cpu frequency and switch
low power mode.
Change-Id: I1621aa65bea989fd12
hikey: support BL2
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2
is the mcu firmware that is used to scale cpu frequency and switch
low power mode.
Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
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| 08b167e9 | 24-May-2017 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: support BL1
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.
Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833
hikey: support BL1
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.
Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>
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| 7c7dffd8 | 03-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
plat/arm: Compile out impossible conditional for AArch32
Since ARM_DRAM2_BASE is above the 32-bit limit, the condition
is always false. Wrap this condition in an ifndef to avoid
warnings during com
plat/arm: Compile out impossible conditional for AArch32
Since ARM_DRAM2_BASE is above the 32-bit limit, the condition
is always false. Wrap this condition in an ifndef to avoid
warnings during compilation.
Change-Id: Ideabb6c65de6c62474ed03eb29df4b049d5316be
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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|
| 9bedc6d3 | 02-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Remove plat_match_rotpk reference
This function was removed long ago. Remove remaining
pragma reference.
Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80
Signed-off-by: dp-arm <dimitris.papast
Remove plat_match_rotpk reference
This function was removed long ago. Remove remaining
pragma reference.
Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| 0851cb24 | 02-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
fvp: Remove unnecessary default case
The default case is impossible to hit as the `power_level`
is already checked earlier. Avoids a clang warning.
Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3
fvp: Remove unnecessary default case
The default case is impossible to hit as the `power_level`
is already checked earlier. Avoids a clang warning.
Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3a8ab
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| c243e30b | 02-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Include missing header in arm_bl2_setup.c
Change-Id: I4108ce8d1fe7d3fd51a5a96d43b9134c23b8399b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com> |
| e715e676 | 24-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #938 from masahir0y/tools_share
Collect headers shared between TF and host-tools into include/tools_share |
| d77b98ca | 24-May-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
mbedtls: Use `MBEDTLS_SHA256_SMALLER` in ARM platforms
This options enables an implementation of SHA-256 that has a smaller
code footprint (~1.6 KB less) but is also ~30% slower. For ARM
platforms,
mbedtls: Use `MBEDTLS_SHA256_SMALLER` in ARM platforms
This options enables an implementation of SHA-256 that has a smaller
code footprint (~1.6 KB less) but is also ~30% slower. For ARM
platforms, code size is currently considered more important than
execution speed in the mbed TLS crypto module.
Added a small note about this option to the documentation of the
authentication framework.
Change-Id: I4c0b221ea5d3466465261316ba07b627fa01b233
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 232c6b34 | 23-May-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
FVP,Juno: switch FVP and Juno to use generic TBBR OID header
The header tbbr_oid.h contains OIDs obtained by ARM Ltd.
so there is no good reason to use platform_oid.h
Signed-off-by: Masahiro Yamada
FVP,Juno: switch FVP and Juno to use generic TBBR OID header
The header tbbr_oid.h contains OIDs obtained by ARM Ltd.
so there is no good reason to use platform_oid.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| bb41eb7a | 22-May-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
cert: move platform_oid.h to include/tools_share for all platforms
Platforms aligned with TBBR are supposed to use their own OIDs, but
defining the same macros with different OIDs does not provide a
cert: move platform_oid.h to include/tools_share for all platforms
Platforms aligned with TBBR are supposed to use their own OIDs, but
defining the same macros with different OIDs does not provide any
value (at least technically).
For easier use of TBBR, this commit allows platforms to reuse the OIDs
obtained by ARM Ltd. This will be useful for non-ARM vendors that
do not need their own extension fields in their certificate files.
The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h
Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by
defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the
backward compatibility.
For clarification, I inserted a blank line between headers from the
include/ directory (#include <...>) and ones from a local directory
(#include "..." ).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 81602a97 | 22-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #939 from dp-arm/dp/AArch32_tbbr
Add TBBR and FWU support for AArch32 |