feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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refactor(st): use %c to display board info

Now that %c is supported in log functions, use it instead of creating a
temporary string in stm32_display_board_info(). This also saves a few
bytes of code

refactor(st): use %c to display board info

Now that %c is supported in log functions, use it instead of creating a
temporary string in stm32_display_board_info(). This also saves a few
bytes of code.

Change-Id: If071ed83b92bd30aec425f5b33f66f87c066dae5
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(arm): prefer GUID-based GPT partition lookup

Add platform overrideable GUID defaults for FWU metadata
and FIP image lookup.
Prefer GUID-based lookup with name fallback and clearer
error handlin

feat(arm): prefer GUID-based GPT partition lookup

Add platform overrideable GUID defaults for FWU metadata
and FIP image lookup.
Prefer GUID-based lookup with name fallback and clearer
error handling.
Use FWU metadata image GUIDs when present to select active
FIP partition

Change-Id: I81c87ad9794dc6e29a4b7f9a121eb2d41c9afa37
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(arm): bound backup GPT spec length

Initialize backup GPT block spec length to the expected table size so
IO reads are bounded and cannot rely on a zero-length placeholder.

Change-Id: I0e628f12e

fix(arm): bound backup GPT spec length

Initialize backup GPT block spec length to the expected table size so
IO reads are bounded and cannot rely on a zero-length placeholder.

Change-Id: I0e628f12ea8be45963748e562f652aaf1466f8f5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(juno): raise BL2 max size for hardened IO checks

Increase Juno PLAT_ARM_MAX_BL2_SIZE to accommodate additional bounds
checking in the BL2 IO/FIP path introduced for the FIP ToC validation
fix.

fix(juno): raise BL2 max size for hardened IO checks

Increase Juno PLAT_ARM_MAX_BL2_SIZE to accommodate additional bounds
checking in the BL2 IO/FIP path introduced for the FIP ToC validation
fix.

Change-Id: I535a4985f3c8c38ccf1277d4eef6c58bf9b1b293
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(k3low): extend BL1 RW region for debug builds

DEBUG=1 builds include larger xlat tables that overflow BL1's 12K RW
region by 4K. Extend BL1_RW_LIMIT by 0x1000 under #ifdef DEBUG and
emit a loud

fix(k3low): extend BL1 RW region for debug builds

DEBUG=1 builds include larger xlat tables that overflow BL1's 12K RW
region by 4K. Extend BL1_RW_LIMIT by 0x1000 under #ifdef DEBUG and
emit a loud make-time warning that this binary is non-functional
(the extended region overlaps MAILBOX_SHMEM).
Also, add an ERROR print to make sure users are aware at boot
that BL1 has been built with DEBUG flag and panic.

NOT intended for production or functional testing.

Change-Id: Iae9453d8c5305e3e88c6e21fa5ac042c9a210d37
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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fix(k3low): add plat_get_image_source stub for BL1

AM62L BL1 never calls load_image (it hands off to ROM via secure
transport and enters WFI), but the generic bl_common.c:load_image
pulls in plat_ge

fix(k3low): add plat_get_image_source stub for BL1

AM62L BL1 never calls load_image (it hands off to ROM via secure
transport and enters WFI), but the generic bl_common.c:load_image
pulls in plat_get_image_source as a required symbol. Add a stub
returning -ENOTSUP to satisfy the linker.

Change-Id: I331ad94dea110a7202d3961119ac690b3c499736
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gau

fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(rk3568): add early CPU reset mechanism to enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software. This commit implements a mechanism to enable the

feat(rk3568): add early CPU reset mechanism to enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software. This commit implements a mechanism to enable the cryptographic
hardware accelerator on the RK3568 platform during early boot. The
function `rockchip_cpu_reset_early` is added and conditionally compiled
via the new build flag `PLAT_RK_CPU_RESET_EARLY`.

Change-Id: Ibe35f9d65bbb5280e71e21979ca1d3bc9b38cae5
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>

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fix(rcar3): change the migrate information for OPTEE-OS

This commit fixes the migration information to fit the OPTEE-OS on
R-Car Gen3. The OPTEE-OS port is always running on the boot core and
is not

fix(rcar3): change the migrate information for OPTEE-OS

This commit fixes the migration information to fit the OPTEE-OS on
R-Car Gen3. The OPTEE-OS port is always running on the boot core and
is not MP capable. Instead of patching the opteed SPD code, duplicate
the spd_pm_ops_t opteed_pm into local spd_pm_ops_t rcar_opteed_pm and
rewrite its .svc_migrate_info with rcar_svc_migrate_info already used
by R-Car Gen3. This now covers both SPD=none and SPD=opteed use cases.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I0dcabd2f1a39232ecd304ad01ea0160874641198

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feat(k3low): add BL1 platform definitions and integration for AM62L

AM62L devices use BL1 to configure DDR4/LPDDR4 before the secondary
bootloader. This patch wires all prior DDR and board patches i

feat(k3low): add BL1 platform definitions and integration for AM62L

AM62L devices use BL1 to configure DDR4/LPDDR4 before the secondary
bootloader. This patch wires all prior DDR and board patches into a
complete, buildable bl1.bin:

- ti_platform_defs.h: add IMAGE_BL1 conditionals for BL1-specific
stack and memory layout definitions.
- platform_def.h: add BL1 SRAM base/size and mailbox address
definitions used by am62l_bl1_setup.c.
- am62l_bl1_setup.c: BL1 platform initialisation — console, DDR
init via the Cadence/TI shim, and WFI-based handoff to the
secondary bootloader.
- platform.mk: add BL1_SOURCES, K3_LPDDR4_SOURCES, update BUILD_PLAT
and PLAT_INCLUDES to compile all DDR and BL1 sources.

Change-Id: I91e8b9e8e43a5560aa688d58e6805a7b5236de44
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

- board_config.c: pad-mux initialisation for MAIN/WKUP UART0 pins,
verified against the AM62L TRM (SPRUJB4A p.3976).
- board_def.h: board-level UART base and clock definitions.
- board_config.h: shared header declaring board_init().

Add the TI-authored AM62L DDRSS platform shim that wraps the Cadence
driver for this SoC:

- am62l_ddrss.c / am62l_ddrss.h: PSC power sequencing and DDR
initialisation flow calling the Cadence CTL/PHY/PI APIs.
- am62lx_ddr_config.c / am62lx_ddr_config.h: register data for the
AM62L DDRSS configuration.
- am62lx_skevm_lp4_50_800.h: machine-generated SK-EVM LPDDR4 register
values produced by the SysConfig DDR tool v0.10.30. This file should
be regenerated via that tool if board or timing parameters change.

New source files are intentionally unreferenced in platform.mk pending
the BL1 integration patch.

board.mk is introduced as a placeholder required by platform.mk's
include directive for BL31 builds; BL1_SOURCES will be added in the
next patch when BL1 support is wired in.

Change-Id: I8aff5eb1c2429646a701dc3b09821318bb6e73b9
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces

feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces the
Cadence IP driver files (lpddr4.c, lpddr4_16bit.c, lpddr4_obj_if.c and
their associated headers) which carry dual copyright (Cadence + TI).

The driver was pruned from ~6800 macros to ~80 with AI-assisted removal
of unused code; the Cadence CTL/PHY/PI API surface remains intact for
review against the User Guides.

These files are intentionally unreferenced in platform.mk pending the
AM62L platform shim in the next patch.

For additional information please check the technical reference
manual at:
https://www.ti.com/lit/pdf/sprujb4

Change-Id: I8b02a6b30e5ea7b1b457cc0a933d8ef232993fa1
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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fix(armada): mv_ddr path may not be a git repo

TF-A CI uses an archive for Marvell DDR code, and not a git repository.
Remove the check for the git repository.
The same change has already been done

fix(armada): mv_ddr path may not be a git repo

TF-A CI uses an archive for Marvell DDR code, and not a git repository.
Remove the check for the git repository.
The same change has already been done for a8k [1].

[1]: 40929c29bffd ("fix(a8k): mv_ddr path may not be a git repo")

Change-Id: I7b5c2367d4ad8ddb6a2ff0b20a5206d972e42e4d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(versal): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to
allow the APU IPI channel to be explicitly selected
at build time, as per the design. This ch

feat(versal): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to
allow the APU IPI channel to be explicitly selected
at build time, as per the design. This change aligns
PLAT_IPI_ID_APU handling with existing IPI ID macros,
enabling platforms to define the APU IPI ID via a build
flag instead of hardcoding it in platform code. This
improves configurability and consistency across platform.

Change-Id: I32a978a1abf8e8d993742cfd1253cfe4a44fd113
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "fix(xilinx): correct node idx for Versal Gen 2" into integration

refactor(qemu): use generic hold pen

Convert QEMU to use the common hold pen helpers.

This is not a functional fix -- QEMU uses HW_ASSISTED_COHERENCY=1
so caches are always coherent and the origina

refactor(qemu): use generic hold pen

Convert QEMU to use the common hold pen helpers.

This is not a functional fix -- QEMU uses HW_ASSISTED_COHERENCY=1
so caches are always coherent and the original 8-byte slots worked.
However, aligning with the common hold pen pattern improves
consistency and removes duplicated logic.

plat_hold_pen_init() is called once from plat_setup_psci_ops() to
write HOLD_STATE_WAIT into every slot and flush to main memory.
Then plat_hold_pen_signal() writes just the target slot with the
entrypoint. Secondaries use the plat_hold_pen_wait_and_jump macro
to poll and branch directly to the entrypoint stored in their slot,
eliminating the mailbox fetch.

Change-Id: I5ca1ca5fb8708024ce8a04fa80403473dcd1e257
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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Merge changes from topic "hold-pen-generic" into integration

* changes:
fix(corstone-1000): use generic hold pen
refactor(platforms): add generic hold pen

Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

Merge "feat(firme): initial commit of FIRME service" into integration

feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic

feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic granule transition function that replaces
the existing delegate/undelegate APIs that GPI_SET uses. It also
updates TRP to use GPI_SET when FIRME is supported.

FIRME spec is here, note that it is ALPHA2 quality so further changes
are to be expected:
https://developer.arm.com/documentation/den0149

Change-Id: I57b8ad7e87a0679e15c8247f8457f91f3254dedb
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (n

fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (not cache-line aligned)
and only wrote GO to the target slot without touching other slots
or flushing to main memory. This is broken because:

1. Secondary CPUs write WAIT from non-cached context (MMU off in BL2)
2. The BL2-to-BL31 transition does dcsw_op_all (flush all caches)
3. This pushes stale cached data over the WAIT values in memory
4. The primary's GO write + DSB is insufficient -- it only ensures
ordering, not visibility to non-cached observers

plat_hold_pen_init() is called once at boot (from
plat_arm_psci_override_pm_ops) to write HOLD_STATE_WAIT into every
cache-line-aligned slot and flush the region. Then
plat_hold_pen_signal() writes just the target slot with the warm
boot entrypoint, flushes it, and issues SEV. Secondaries use the
plat_hold_pen_wait_and_jump macro to poll and branch directly to
the entrypoint stored in their hold slot.

Change-Id: I8fc533650c663700dab9bf47c0a79d9bb1236b17
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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refactor(platforms): add generic hold pen

Introduce a common hold pen implementation for SMP secondary CPU
bring-up. Each core has a cache-line-aligned hold_slot struct
whose 'entry' field holds HO

refactor(platforms): add generic hold pen

Introduce a common hold pen implementation for SMP secondary CPU
bring-up. Each core has a cache-line-aligned hold_slot struct
whose 'entry' field holds HOLD_STATE_WAIT (all-ones sentinel)
while the core should keep polling, or the warm boot entrypoint
address when it should go.

plat_hold_pen_init() sets all slots to HOLD_STATE_WAIT and flushes
them to main memory. This is called once during boot to
establish a known-good state, overwriting any stale cached data
left by earlier boot stages (e.g. a BL2 dcsw_op_all).

plat_hold_pen_signal() writes the entrypoint into the target slot,
flushes it, and issues SEV.

The plat_hold_pen_wait_and_jump assembly macro provides the
secondary CPU polling loop for both AArch64 and AArch32.

Change-Id: Id7322cb9e8caa6a750348d194b4db66e2a515623
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runt

Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runtime): use arm_gicr_base_addrs for sp-min

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