Merge "feat(mt8196): add booker driver" into integration

feat(mt8196): add booker driver

The booker tag cache will be lost when mcusys off, so it needs to be
flushed to DRAM during the power-off sequence.

Signed-off-by: Runyang Chen <runyang.chen@mediate

feat(mt8196): add booker driver

The booker tag cache will be lost when mcusys off, so it needs to be
flushed to DRAM during the power-off sequence.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: I71ddd1f9d1613ce4f5bc10103683b504573e2842

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fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout is not included when building FVP.
FVP's do not require a physical carveout to
emulate MTE, so we can save the memory.
- Add memory map diagrams to platform_def.h
- Tidy up existing memory map macros.

Change-Id: I4d31aa27e470344d4ed6469939331d0e2ced9d54
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(juno): restrict measured boot to a single algo" into integration

Merge "fix(tegra): fix receiving boot params on Tegra210" into integration

Merge "feat(versal2): support alternate core as primary (non-cpu0)" into integration

fix(tegra): fix receiving boot params on Tegra210

Commit 0b9f05f assumes that all platforms set RESET_TO_BL31 and
implement custom boot param handling. Which is not the case for
Tegra210. This adds

fix(tegra): fix receiving boot params on Tegra210

Commit 0b9f05f assumes that all platforms set RESET_TO_BL31 and
implement custom boot param handling. Which is not the case for
Tegra210. This adds back direct bootloader parameter handling for non
RESET_TO_BL31 platforms.

Change-Id: I23f530a09163c3bf641dc6e8c48ea2864a187514
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>

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fix(intel): restore overlap-safe memcpy_s to prevent SoCFPGA BL2 hang

Previously, memcpy_s() in common/lib/libc was changed to
use memcpy/__builtin_memcpy to allow compiler optimizations
(FEAT_MOPS

fix(intel): restore overlap-safe memcpy_s to prevent SoCFPGA BL2 hang

Previously, memcpy_s() in common/lib/libc was changed to
use memcpy/__builtin_memcpy to allow compiler optimizations
(FEAT_MOPS / inline sequences). While safe for most
platforms, this breaks SoCFPGA early boot because handoff data
can overlap in memory.

The change causes BL2 to hang, preventing UART initialization.

This patch restores overlap safety by replacing the memcpy call
with memmove/__builtin_memmove when available,
while preserving bounds checking.
This ensures SoCFPGA BL2 handoff functions correctly without
impacting other platforms.

Change-Id: I89e16cfe044ecb3abde062cbeaa8b0ca247910b5
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(layerscape): unlock write access SMMU_CBn_ACTLR" into integration

fix(rk3576): shorten names to fit into the allocated space

The SCMI spec's CLOCK_ATTRIBUTES command specifies the `clock_name` part
of the return value as 16 long. Three of rk3576's names are a char

fix(rk3576): shorten names to fit into the allocated space

The SCMI spec's CLOCK_ATTRIBUTES command specifies the `clock_name` part
of the return value as 16 long. Three of rk3576's names are a character
over, which GCC15 warns about truncating the NULL terminator. So shorten
the names a tiny bit to prevent this.

Change-Id: I20c97011f906018b67b1291753ce45fa48bc84a7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(juno): restrict measured boot to a single algo

Juno is already quite space constrained. This makes enabling all
algorithms provided by Mbed-TLS by default a no-go. Similar to TC,
constrain the b

fix(juno): restrict measured boot to a single algo

Juno is already quite space constrained. This makes enabling all
algorithms provided by Mbed-TLS by default a no-go. Similar to TC,
constrain the board to a single algorithm when measured boot is enabled.

Change-Id: I848241b75a6c791c2bdfa42434de446c9e8c75de
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the buil

feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the build switches from `cortex_a35.S` to
`cortex_a320.S`, maintaining compatibility with existing A35-based
designs.

Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM
on Cortex-A320 platforms so U-Boot and other non-secure software
can safely access these regions:

* **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB),
attrs `MT_DEVICE | MT_RW | MT_NS`
* **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB),
attrs `MT_MEMORY | MT_RW | MT_NS`

Enable GICv3 with GIC-600 when building for Cortex-A320 (retain
GICv2/GIC-400 for Cortex-A35):

* Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use
the Cortex-A320 MPIDR_EL1 affinity layout.
* Add an A320-specific core-position routine in assembly guarded by
`CORSTONE1000_CORTEX_A320`.
* Switch to the GICv3 driver with GIC-600 extensions: update GIC base
addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`,
`GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`.

These changes prepare the platform for Cortex-A320 integration and
ensure correct GIC configuration and secondary-core bring-up, while
preserving A35 behavior.

Change-Id: Ief03dd528e67918e160d5b42ad1344b0ba3440f8
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Signed-off-by: Michael Safwat <michael.safwat@arm.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the p

feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the primary and
gate secondary core startup inline to existing implementation for
secondary cores.

Change-Id: I6a5d76f23d4d4c4139d95bbaf55edf1244f2dbfe
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I9375fad3,Ie072f9fe into integration

* changes:
refactor(fvp): use SZ_* defs fr event log
fix(rme): increase worst-case event size

Merge "fix(fvp): fully remove FVP_Foundation" into integration

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Sign

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <h

refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case siz

fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case size to account for this.

Change-Id: Ie072f9fe1ea5617c030556fae4c8c893cfefc4e0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "hm/evlog" into integration

* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile me

Merge changes from topic "hm/evlog" into integration

* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile measured boot
refactor(juno): use crypto-agile measured boot
refactor(rpi3): use crypto-agile measured boot
refactor(fvp): use crypto-agile measured boot
feat(measured-boot): enable dynamic hash provisioning
feat: add TPM/TCG hashing helper to crypto module
chore: bump event log library

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Merge changes I4d50d138,Ie16b2e40,I574893fa into integration

* changes:
refactor(tpm): remove TPM code from TF-A
feat(tpm): changes to support TPM lib
feat: add libtpm submodule

refactor(drtm): use crypto-agile measured boot

Update the DRTM boot flow to use the crypto-agile API. Replace the
previous single-algorithm hash configuration with dynamic algorithm
selection. Align

refactor(drtm): use crypto-agile measured boot

Update the DRTM boot flow to use the crypto-agile API. Replace the
previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I22930440476895c23dbd4e04502757d2f6726e33
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(imx): use crypto-agile measured boot

Update the i.MX measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selectio

refactor(imx): use crypto-agile measured boot

Update the i.MX measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: Ia60b5c927c1d7e4262562fb1eee2e4602b832e78
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(qemu): use crypto-agile measured boot

Update the QEMU measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selecti

refactor(qemu): use crypto-agile measured boot

Update the QEMU measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: Iab276b88ce85675374aa2c104cbd0aa907be2acb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(juno): use crypto-agile measured boot

Update the Juno measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selecti

refactor(juno): use crypto-agile measured boot

Update the Juno measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I9bca6c9f2a6f3507cea5ced7c2ab83ee5a4c1a91
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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