Merge pull request #1412 from masahir0y/uniphier

uniphier: fix CCI-500 connection for LD20

rockchip: Move stdint header to the offending header file

The stdint header was introduced to rk3399's plat_sip_calls.c in order
to fix missing stdint definitions. However, ordering headers
alphabet

rockchip: Move stdint header to the offending header file

The stdint header was introduced to rk3399's plat_sip_calls.c in order
to fix missing stdint definitions. However, ordering headers
alphabetically caused the fix to be ineffective, as stint was then
included after the offending header file (dfs.h).

Move the stdint include to that header to properly fix the issue.

Change-Id: Ieaad37a7932786971488ab58fc5b169bfa79e197
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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SPM: Treat SP xlat tables the same as others

The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping B

SPM: Treat SP xlat tables the same as others

The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping BL31's general purpose memory. They will be mapped with
the same attributes as them, which is fine.

The explicit alignment constraint in BL31's linker script to pad the
last page of memory allocated to the Secure Partition's translation
tables is useless too, as page tables are per se pages, thus their
end address is naturally aligned on a page-boundary.

In fact, this patch does not change the existing behaviour. Since
patch 22282bb68a31 ("SPM: Move all SP-related info to SP context
struct"), the secure_partition.c file has been renamed into sp_xlat.c
but the linker script has not been properly updated. As a result, the
SP translation tables are not specifically put at the start of the
xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__
symbols have the same value, the size of the resulting mmap_region
covering these xlat tables is 0 and so it is ignored.

Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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LOAD_IMAGE_V1: Align BL2 memory layout struct to 8 bytes

In LOAD_IMAGE_V1 (i.e when LOAD_IMAGE_V2=0) the bl2_tzram_layout is,
by default, assigned to the bl1_tzram_layout->free_base which is
dynamic

LOAD_IMAGE_V1: Align BL2 memory layout struct to 8 bytes

In LOAD_IMAGE_V1 (i.e when LOAD_IMAGE_V2=0) the bl2_tzram_layout is,
by default, assigned to the bl1_tzram_layout->free_base which is
dynamically calculated based on the images loaded in memory. There is a
chance that the bl2_tzram_layout will be assigned a value not aligned to
8 bytes. This patch rounds up the free_base value for the required
alignment.

This doesn't happen in LOAD_IMAGE_V2 because the bl2_tzram_layout is
assigned by default to the bl1_tzram_layout->total_base, which is
aligned.

Change-Id: Idc583e7dad993d02ac6791797406118c96f83fa1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Fix MISRA Rule 5.7 Part 2

Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

To prevent violation of directive 4.5 having variable name channel
in css_pm_scmi.

Fix MISRA Rule 5.7 Part 2

Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

To prevent violation of directive 4.5 having variable name channel
in css_pm_scmi.c not being typographically ambiguous change macro
argument CHANNEL in css_mhu_doorbell.h change argument to _channel
to fit with our convention which is a permitted exception of
directive 4.5 for this project

Rule 5.7: A tag name shall be a unique identifier

Fixed for:
make LOG_LEVEL=50 PLAT=juno

Change-Id: I147cdb13553e83ed7df19149b282706db115d612
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Fix MISRA Rule 5.3 Part 5

Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope sh

Fix MISRA Rule 5.3 Part 5

Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope

Fixed For:
make LOG_LEVEL=50 PLAT=juno

Change-Id: I575fbc96e8267f2b075e88def1f6e3185394613a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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uniphier: fix CCI-500 connection for LD20

The slave ports of LD20 CCI-500 are connected as follows:

S0: CA53
S1: CA72

Be careful because the slave interface is not arranged in the
cluster numb

uniphier: fix CCI-500 connection for LD20

The slave ports of LD20 CCI-500 are connected as follows:

S0: CA53
S1: CA72

Be careful because the slave interface is not arranged in the
cluster number order (CA72: cluster 0, CA53: cluster 1).

Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com>
Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>

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Merge pull request #1397 from dp-arm/dp/cortex-a76

Add support for Cortex-A76 and Cortex-Ares

Revert "Code change to fix small bugs"

Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default

The upcoming patch that adds dynamic mitigation for Cortex-A76
requires that DYNAMIC_WORKAROUND_CVE_2018_3639=1. On FVP, we pull in
all the

Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default

The upcoming patch that adds dynamic mitigation for Cortex-A76
requires that DYNAMIC_WORKAROUND_CVE_2018_3639=1. On FVP, we pull in
all the CPU files into the build which means there will be a build
failure if DYNAMIC_WORKAROUND_CVE_2018_3639=0.

Change-Id: I2e781cbeafbf5d16eaabf76a1677e0c9f81269d2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Add AMU support for Cortex-Ares

Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Add support for Cortex-Ares and Cortex-A76 CPUs

Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in har

Add support for Cortex-Ares and Cortex-A76 CPUs

Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.

Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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Merge pull request #1389 from danielboulby-arm/db/bugfix

Code change to fix small bugs

Juno: Bump up the BL1-RW size

This patch bumps up the BL1-RW size for Juno and at the same time reduces
the BL2 size when TBB is enabled, TF_MBEDTLS_KEY_ALG=rsa+ecdsa. The BL2
size for this config i

Juno: Bump up the BL1-RW size

This patch bumps up the BL1-RW size for Juno and at the same time reduces
the BL2 size when TBB is enabled, TF_MBEDTLS_KEY_ALG=rsa+ecdsa. The BL2
size for this config is reduced as it was observed that the peak memory
usage is only reached when SPD=opteed and the dual rsa+ecdsa support is
not needed for this case.

Change-Id: Ia9009771b5cfd805e9cc75410aabb7db99fc2fbc
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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ARM platforms: Move BL31 below BL2 to enable BL2 overlay

The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expe

ARM platforms: Move BL31 below BL2 to enable BL2 overlay

The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.

This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
* When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
* When BL2_AT_EL3=1 for BL2

The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.

Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Remove duplicate weak definition

The weak pragma was assigned twice to the bl2_plat_handle_post_image_load
definition both in plat/common/ and in plat/arm/common/ this was an error as
it should have

Remove duplicate weak definition

The weak pragma was assigned twice to the bl2_plat_handle_post_image_load
definition both in plat/common/ and in plat/arm/common/ this was an error as
it should have only have been defined in plat/common

Change-Id: Id85e14c699cb09ed998d1677f2a172e760911918
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge pull request #1395 from antonio-nino-diaz-arm/an/spm-refactor

SPM: Refactor codebase

plat/arm: SPM: Force BL31 to DRAM when SPM is used

BL31 is running out of space, and the use-case of SPM doesn't require it
to be in SRAM. To prevent BL31 from running out of space in the future,
mo

plat/arm: SPM: Force BL31 to DRAM when SPM is used

BL31 is running out of space, and the use-case of SPM doesn't require it
to be in SRAM. To prevent BL31 from running out of space in the future,
move BL31 to DRAM if SPM is enabled.

Secure Partition Manager design document updated to reflect the changes.

Increased the size of the stack of BL31 for builds with SPM.

The translation tables used by SPM in Arm platforms have been moved back
to the 'xlat_tables' region instead of 'arm_el3_tzc_dram'. Everything is
in DRAM now, so it doesn't make sense to treat them in a different way.

Change-Id: Ia6136c8e108b8da9edd90e9d72763dada5e5e5dc
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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FVP: Add dummy configs for BL31, BL32 and BL33

This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP.
The config files are placeholders and do not have any useful bindings
defined

FVP: Add dummy configs for BL31, BL32 and BL33

This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP.
The config files are placeholders and do not have any useful bindings
defined. The tos_fw_config is packaged in FIP and loaded by BL2 only
if SPD=tspd. The load address of these configs are specified in tb_fw_config
via new bindings defined for these configs. Currently, in FVP, the
soc_fw_config and tos_fw_config is loaded in the page between BL2_BASE
and ARM_SHARED_RAM. This memory was typically used for BL32 when
ARM_TSP_RAM_LOCATION=tsram but since we cannot fit BL32 in that
space anymore, it should be safe to use this memory for these configs.
There is also a runtime check in arm_bl2_dyn_cfg_init() which ensures
that this overlap doesn't happen.

The previous arm_dyn_get_hwconfig_info() is modified to accept configs
other than hw_config and hence renamed to arm_dyn_get_config_load_info().
The patch also corrects the definition of ARM_TB_FW_CONFIG_LIMIT to be
BL2_BASE.

Change-Id: I03a137d9fa1f92c862c254be808b8330cfd17a5a
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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FVP: Enable capability to disable auth via dynamic config

This patch adds capability to FVP to disable authentication dynamically
via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 pa

FVP: Enable capability to disable auth via dynamic config

This patch adds capability to FVP to disable authentication dynamically
via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses
the TB_FW_CONFIG for the `disable_auth` property and invokes the
`load_dyn_disable_auth()` API to disable authentication if the
property is set to 1. The DYN_DISABLE_AUTH is enabled by default for
FVP as it is a development platform. Note that the TB_FW_CONFIG has to
be authenticated by BL1 irrespective of these settings.

The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup()
rather than in bl2_platform_setup() as we need to get the value of
`disable_auth` property prior to authentication of any image by BL2.

Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1369 from sivadur/xilinxdiff

Xilinx platform mangement related changes

Merge pull request #1384 from rockchip-linux/for_m0_patch

for rk3399 suspend/resume

zynqmp: Add wdt timeout restart functionality

This patch adds support to restart system incase of wdt
timeout.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, dis

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, display
EG/EV as a part of string. The PL powerup status will
be filled by pmufw based on PL PROGB status in the
9th bit of version field.This patch also used IPI
to get this info from pmufw instead of directly accessing
the registers. Accessing this info from pmufw using
IPI fixes the issue of PMUFW access denied error for
reading IPDISABLE register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

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zynqmp: Add new API for processing secure images

This patch adds new API for processing secure images. This API
is used for authentication and decryption of secure images using
xilsecure in pmufw.

zynqmp: Add new API for processing secure images

This patch adds new API for processing secure images. This API
is used for authentication and decryption of secure images using
xilsecure in pmufw.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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