Merge "fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)" into integration

Merge changes from topic "bk/fvp_r" into integration

* changes:
fix(tbbr): remove tbbr_cot_bl1_r64.c
fix(xlat): remove xlat_mpu

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): ad

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): add support for TI mailbox driver
refactor(ti): move out k3/common to ti/common
refactor(ti): introduce ti_bl31_setup
refactor(ti): add the sec hdr to the ti sci msg
refactor(ti): rename the k3_sec_proxy_chan_id
refactor(ti): rename the sec_proxy functions
refactor(ti): add top level ti_sci transport layer
refactor(ti): move TI SCI and sec proxy to drivers

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feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed

feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed via the Firmware Handoff framework.

Also, adjust the maximum BL32 size calculation to use
PLAT_ARM_FW_HANDOFF_SIZE when TRANSFER_LIST is enabled.

Change-Id: I82032b1cebf8b37ff24dde4f2d07f7aaede33eb6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry poin

feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry point info to enable booting in aarch32 mode. In SP-MIN
process expected data directly from the transfer list in secure memory.

Change-Id: If0417cdd4c47b772332eb6fd4b71ef0ea474f0fa
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appea

fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appear to be finished.

Change-Id: I76499b92ca4368651330f17dc80803991158cc36
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Kar

fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementatio

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementation is aligned with the existing PSCI reset interface.

This implementation allows the external users to define
platform-specific actions for warm/soft reset within the reset2
handler if needed.

Change-Id: Ibb937e4c0994a29b45b9b19f8addad56fe7e7e23
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common f

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common folder

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fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link er

fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link error
("region `RAM' overflowed by 4096 bytes").

* Resolved by increasing PLAT_ARM_MAX_BL2_SIZE by 4KB to accommodate
the larger image.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie9d411c1207801436d8cffcf72fec2752371eb69

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Merge "fix(plat): remove fvp_r" into integration

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two pla

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two places in the build system did not support this, instead were just
checking for a value of "1".

Fix the AArch32 check and build the FVP specific handler routine when
the value is not "0", instead of relying on it to be exactly "1".

Change-Id: I1acd3ed6d2a461d541b9bf57e4aac9c0798ab56b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(arm): resolve misra rule R11.6 violation" into integration

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some high

feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some highlights of AM62L SoC are:
- Single to Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem
- 16-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
- Multiple low power modes support, ex: Deep sleep and RTC+DDR
- Mailbox transport layer for TI SCI

For more information check out our Technical Reference Manual (TRM)
which is loacted here:

https://www.ti.com/lit/pdf/sprujb4

Change-Id: I9d7c707b5b220c5ec13bd2de67f872b3da3c308a
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): introduce PSCI Driver for AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development

There is enough

feat(ti): introduce PSCI Driver for AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development

There is enough deviation from the previous K3 gen SoCs with regards to
how the PSCI functionality looks like on this device. For example, it
no longer does reset or LPSC turn ON/OFF operations using any external
Device Management entity like it did earlier.

The actual power ON/OFF operations will be implemented in a later stage
once all the PM related drivers are integrated. Such places in this
driver have been marked as TODO and will be replaced with actual call
to power on/off the cores at a later point.

This warranted the addition of a new am62l_psci driver for the AM62L
family of devices. For further details of how this new device looks
like, refer to the TRM [1].

[1] https://www.ti.com/lit/pdf/sprujb4

Change-Id: Ic53096e7bbc25fa55386ac4b6bef364dd6d0cf3b
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we

refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we can move the previously
created ti_bl31_setup file into the new location so it can be shared
across multiple TI SoCs when need comes.
With this, also update all copyright dates.

Change-Id: Ie4365e32cd3b4b5870fe2cd03843400506e46265
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(mt8189): add GPIO support

- Add GPIO support for MT8189.

Change-Id: I2d140b32eef8c05aba9170bf4af894ed43d52978
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>

feat(mt8189): initialize platform for MT8189

- Add basic platform setup.
- Add MT8189 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

Change-Id: Id59a

feat(mt8189): initialize platform for MT8189

- Add basic platform setup.
- Add MT8189 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

Change-Id: Id59ae9265983defb46e27befabfd5c30b2b4a5a6
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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refactor(ti): introduce ti_bl31_setup

There maybe a lot of reuse between platforms for bl31_setup in future
which may require us to have a common bl31 setup driver for TI.
The ti_bl31_setup is expec

refactor(ti): introduce ti_bl31_setup

There maybe a lot of reuse between platforms for bl31_setup in future
which may require us to have a common bl31 setup driver for TI.
The ti_bl31_setup is expected to contain all the reusable bits
and the soc_bl31_setup can have the custom soc init functionality
like the mmap regions and any special sequences needed at
device boot
While at it, also fix the path of the reference to the kernel doc
for booting.

Change-Id: Ie574f08cf3ba75362c45f85306499061ef89c964
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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refactor(ti): add top level ti_sci transport layer

The TI SCI transport header will allow us to abstract all transport
related calls from the actual medium of transport which can vary
from device to

refactor(ti): add top level ti_sci transport layer

The TI SCI transport header will allow us to abstract all transport
related calls from the actual medium of transport which can vary
from device to device.
For eg. it is sec proxy for current TI K3 devices, but in future it
maybe mailbox like in the TI AM62L.
With this change, we no longer need to include anything from the IPC
folder, so drop it from plat_common.mk

Change-Id: Ic99209688cf69f20e694e31e553ce4ec74254669
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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refactor(ti): move TI SCI and sec proxy to drivers

Prepare to support more devices and abstract TI SCI and it's transport
layers. This refactor will help keep things clean when new ipc drivers
get a

refactor(ti): move TI SCI and sec proxy to drivers

Prepare to support more devices and abstract TI SCI and it's transport
layers. This refactor will help keep things clean when new ipc drivers
get added.

Change-Id: I05673f379b1398c0b6a2bd9e1b5392165d12f151
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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Merge "fix(arm): resolve build issue with ARM_ROTPK_LOCATION=regs option" into integration

refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa

refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa0e891f080e58f21e6e79551d2a19e0
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge changes from topic "upstream-stm32mp257d-ultra-fly-sbc" into integration

* changes:
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
feat(fdts): add support for STM32MP257D

Merge changes from topic "upstream-stm32mp257d-ultra-fly-sbc" into integration

* changes:
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
feat(fdts): add support for STM32MP257D-based ultra-fly-sbc board
feat(fdts): add dual-ranked LPDDR4 config for STM32MP2

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